Abstract: A method and a computer for execution of the method. As part of executing a stream of instructions, a series of memory loads is issued from a computer CPU to a bus, some directed to well-behaved memory and some directed to non-well-behaved devices in I/O space. Computer addresses are stored of instructions of the stream that issued memory loads to the non-well-behaved memory, the storage form of the recording allowing determination of whether the memory load was to well-behaved memory or not-well-behaved memory without resolution of any memory address stored in the recording.
Type:
Grant
Filed:
October 28, 1999
Date of Patent:
May 28, 2002
Assignee:
ATI International SRL
Inventors:
John S. Yates, Jr., David L. Reese, Korbin S. Van Dyke