Abstract: A keyboard controller is used to drive the PDEN pins on DIMMs. A PC has a keyboard controller with a plurality of programmable input/output (I/O) pins. The state of the programmable I/O pins can be set by software. The pins are coupled to individual PDEN pins on the DIMMs. When the programmable I/O pins are activated, the PDEN pins are driven active and each DIMM outputs a signal indicating its characteristics. The signals are latched and stored for use by a memory controller.

Abstract: A video port interface that determines the amount and type of incoming data by reading information from certain memories. A first memory indicates a first format of the incoming data. A second memory indicates a second format of the incoming data. Finally, a third memory indicates a number of lines of the first format that will be received. The video port interface reads all three memories at the beginning of each frame, then counts incoming lines until it reaches the line indicated by the third memory. At the end of that line, the video port interface switches from processing the data in the first format to processing data in the second format.

Abstract: An apparatus for capturing and decoding the teletext data from a television signal and displaying the teletext data, along with the video picture, in a windowing environment on the monitor of a personal computer system. The teletext data decoder retrieves the lines of teletext data stored in the frame buffer with the rest of the video frames, decodes the teletext data in software and stores the teletext characters directly in system memory for further processing and display in user-defined windows on the PC monitor.

Abstract: An SDRAM memory controller that provides both burst four and single data transfers while keeping the SDRAM in burst four mode. A memory controller uses a DQMB?7:0! signal and a precharge command to stop the transference of data on the data bus during the time that the last 3 data elements would have been transferred. Specifically, during a single read, DQMB?7:0! is set high for two clock cycles causing the data bus to float during the time that the second and third data elements would have been on the bus. During a single write, DQMB?7:0! is set high for two clock cycles thereby preventing the second and third data elements from being written to memory. During a read, the precharge command causes the bus to float during the time the fourth element would have been on the bus. During a write, the precharge command prevents the fourth data element from being written.

Abstract: A computer system having a unified memory architecture (UMA) with a central SDRAM memory can be accessed by multiple devices. Arbitration logic receives and arbitrates among the memory requests. The memory controller indicates when the arbitration logic may issue a grant. The memory controller has two arbitration points during a memory cycle, an early one and a late one. A central processing unit (CPU), or other device, that misses the early arbitration point can still get memory access during the memory cycle by submitting a memory request before the late arbitration point.

Abstract: An automatic step generator that monitors and corrects the sampling rate in a video signal. The invention isolates a sampling window in the prevailing sampling rate, the window advantageously being 144 lines for NTSC, or 231 lines for PAL, or some other preselected window wherein the sample count therein at an ideal sampling rate approximates an integer power of 2. The invention then calculates the numeric difference between that ideal sample count in the window and the preselected integer power of 2. The actual sample count in the window is then determined, and is adjusted by the numeric difference between the ideal count and the integer power of 2. Variations in this adjusted actual sample count and the integer power of 2 will thus represent variations between the actual sampling rate and the ideal sampling rate. A step value to correct the actual sampling rate to achieve the ideal rate may then be derived by dividing the adjusted actual sample count by the integer power of 2.

Abstract: A precise current cell for a digital-to-analog (D/A) convertor circuit is designed to compensate for manufacturing process variations. The cell uses a cascoded transistor chain to control the output voltage and isolate voltage supply noise. An external (off-chip) bias current is fed into a cascoded biasing string of eight transistors, which are further mirrored to the current cell itself. The biasing scheme accounts for manufacturing process variations in the chip, which leads to very precise current being replicated at the output of the D/A circuit. Current steering and an improved shunt path within the current cell minimizes voltage swings during switching of the current cell. This allows for faster switching of the cell while minimizing noise coupling due to the voltage swings. The current cell also has an associated biasing stage. This biasing stage allows for improved matching within the current cell, resulting in improved accuracy of conversion.

Abstract: An arbitration controller that temporarily raises the priority of a graphic device's HWM request above that of the BitBLT engine while that device's LWM request is being served. In this manner, the BitBLT engine cannot interrupt the transfer of data to the graphics device. Each device capable of issuing memory access requests is categorized into one of four classes. The LWM requests are the highest priority requests, followed by CPU memory access requests, then BitBLT engine requests, and finally by HWM requests. When a LWM request is granted, the requesting device's HWM request is elevated to a priority between the CPU and the BitBLT engine. Once the LWM request is complete, the HWM request is served until either it completes, the CPU issues a memory access request, or another LWM request occurs.

Abstract: A method of establishing communications between a first communication station and a second communication station comprising the steps of: storing a communication originate packet in the first station; storing a communication answer packet responsive to the originate packet in the second station; transmitting the originate packet to the second station from the first station; detecting the originate packet in the second station; transmitting the answer packet from the second station to the first station upon receipt of some but not all of the originate packet; and, establishing communications between the first and second station in response to receipt by the first station of the answer packet.

Abstract: There is disclosed a message formatting arrangement which allows messages from a central processor to be distributed over a bus to a plurality of remote processors using a single address presentation for any message without regard to the byte length of the message. Each message consists of a variable number of sub-messages each having a 3-bit qualifier which specifies the sub-message type. Each remote processor is capable of determining the length of each sub-message depending jointly upon the value of the qualifier and upon the context byte which precedes each group of sub-messages. The remote processors having the capability of skipping over a variable number of idle frames without beginning to process a new message.

Abstract: Unified messaging is a concept that provides for a single electronic mailbox for different types of messages. The mailbox can be on a user's host computer, PBX, PC, etc., and the user has consistant facilities available to originate, receive and manipulate messages. Messages can be translated from one media to another for reception, and a single message may be composed of parts that use different native media. The message recipient has a single controllable point of contact where all messages can be scanned and/or viewed.

Abstract: A system is disclosed for completing communication connections from end-users served by a connectionless (broadcast) type system in a manner which allows expansion of the calling area beyond the immediate physical limitations of the broadcast media. The system is based upon a device for mediating between the connectionless system and a connection oriented system. The device creates logical local area networks interconnectable by the connection oriented system. Calling user identification is used in conjunction with call completion data stored in a central memory for controlling all interconnections.

Abstract: Electro-static discharge is a problem with high-speed data even when using coaxial cables. Primarily, this problem arises at the terminal ends of the circuit where connections are made using separate coaxial cables for connecting to various pieces of equipment thereby allowing voltages to be induced differently in each such cable. This problem can be overcome by combining a portion of each cable such that the shield around each signal carrying wire remains intact while also being solidly in contact with the shield from the other wire. The cable is constructed by removing the outer insulation from a section of two single coaxial cables, electrically connecting together the exposed shields of each cable at both ends of the exposed section and reinsulating the abutted cables so that the shields remain in contact along their entire length.

Abstract: There is disclosed a call announcement circuit arranged for connection to a communication system via a voice (or data) path and also via a separate control channel. Using this arrangement, the system main processor can control the message delivery capacity of the announcement circuit since the circuit has direct access to the internal system buses. This configuration allows detailed control of the announcement circuit on channels separate from the communication channel.

Abstract: A dual mode disk controller is disclosed for use between a host processor and its storage medium for controlling data transfer to and from the storage medium. The data is formatted on the medium in two distinct formats, one capable of bulk fast transfers useful in a swapping operation, and the other capable of periodic slower transfers as is acceptable for file retrieval. The disk controller is designed having a small fast buffer memory for accepting information from the storage medium. File transfer data is transferred immediately without host CPU intervention, to a larger cache memory. The host CPU accesses the fast buffer memory periodically to retrieve swap transfer data while only accessing the larger cache memory when it needs to retrieve the file formatted information.

Abstract: A time division communication system having peripheral devices controlled om a port circuit is arranged such that the port circuit may have assigned to it a variable number of time slots for any peripheral device associated therewith. Each port circuit has a microprocessor control device which is capable of controlling communication to or from the port circuit over the system time division bus or to and from the port circuit and the peripheral over a variable number of time slots, none of which are preassigned to the port circuit.

Abstract: In many situations, contiguous data is not stored at contiguous locations within a memory. This fact alone causes an increase in processor time for retrieval purposes or the intervention of a memory management unit of some type. The situation is compounded when large amounts of data must be obtained from the memory or stored in the memory in real time. This problem is addressed by arranging a dual ported memory between the main memory and the processor and transferring the desired data into the dual ported memory. A pair of buffers are then used for each channel having access to the memory. While one buffer is being read, the other is being loaded. This structure also allows multiple devices to access the single main memory substantially simultaneously.

Abstract: There is disclosed a call announcement circuit integrated into the switching network of a PBX switching system such that the announcement board resides in one of the port slots and has direct access to the internal system buses. The circuit can handle many separate announcements each stored at a selectable compression ratio. Each such announcement can be recorded or played in any of the time slots under processor control. This configuration allows tradeoffs between storage capacity and compression ratio (i.e., speech clarity) and also allows messages to be played on any line or to any station via the communication bus and the selected time slot.

Abstract: The severity of the problems of transmitting high speed data over a regular twisted wire pair are legendary. These problems arise from a variety of conditions, including the capacitance of the wire (which increases with length) and the propensity of unshielded wire to pickup high induced voltages. An arrangement is disclosed that is suitable for short, as well as long, wire distances and which also effectively eliminates the interference problem caused by induced voltages, including those causes by electrostatic discharge. This arrangement passes two twisted wire pairs through a series of ferrite cores. The twisted wire pairs coming out of the ferrite cores are terminated such that one of the pairs is connected to ground while the signal carrying twisted pair is connected to a small signal balun coil, pulse shaping circuit and low pass filter.

Abstract: There is disclosed an asynchronous pulse catching circuit that, for each edge of the variable frequency input, regardless of duty cycle, will provide a pulse, synchronized to a high speed clock. There is also disclosed a pulse comparison circuit consisting of a state machine that provides slip detection between the variable input frequency and a reference input frequency. The circuit provides separate outputs indicating positive and negative slip.