Abstract: In an optical communication system, in order to reduce simultaneously both second and third harmonic distortion in a light beam from a modulated semiconductor laser, a nonlinear interferometric deivce--such as a Fabry-Perot etalon--is inserted in the path of the beam. The parameters of the interferometric device--such as its phase and finesse--are selected such that, for a suitable laser bias current, the second and third harmonics produced by nonlinearities of the laser (plus nonlinearities of the transmission medium such as an optical fiber, if any, through which the beam propagates from source to receiver) are significantly compensated by nonlinearities of the interometric device.

Abstract: A grid structure for the positive electrode of a lead-acid battery cell is composed of several substructures (modules), typically having mutually identical geometric designs. Each of the substructures includes a plurality of metallic members having closed geometric shapes, each contained within another, which satisfy a specific growth ratio relationship, namely, that the ratio of the surface area to cross-section area of any member is no greater than such ratio for a member contained within it. In a preferred embodiment, each such substructure is composed of a plurality of concentric rectangles, each (except the outermost) contained within another. Each rectangle is formed by four lead (or lead alloy) rod-like strips.

Abstract: The span of an optical dispersion-limited fiber for propagating optical pulses is improved by simultaneously chirping and amplifying the stream by means of a saturated semiconductor laser amplifier. The chirp causes a compression of the pulses as they propagate through an initial portion of the fiber, whereby the span of the fiber is increased.

Abstract: A low impedance class AB buffer stage in complementary transistor technology has its quiescient current stabilized and its operation thereby made more reliable by means of suitable error op-amps that are supplied with transistor feedback loops which are connected to the stage's output terminal through resistors. In addition, for full rail-to-rail output voltage capability, transistor switching devices are added to turn off current through either of the resistors when the output voltage approaches the voltage of either power rail, and also a pair of serially rail-to-rail connected transistor is connected in parallel with the feedback loops.

Abstract: In a fiber-optic communication system, a polarization independent semiconductor optical amplifier structure is achieved by tailoring the height-width aspect ratio of its active region to a value at least close to unity and at the same time using a laser cavity structure in which the end mirrors are buried in the semiconductor body in which the optical amplifier structure is built.

Abstract: Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon carrier, and depositing the gold on the silicon dioxide layer.

Abstract: A three or four-port electromagnetic radiation signal beam switching arrangement, such as for simple optical re-routing or for Local Area Network (LAN) loop switching, is achieved with a moving deflecting element having a planar deflecting surface that is constrained to move parallel to itself, into and out of the signal beam. The arrangement can be fabricated in a silicon optical workbench technology.

Abstract: A hot electron transistor (HET) comprising features that can result in substantially improved device characteristics is disclosed. Among the features is a highly doped (typically more than about 10.sup.20 cm.sup.-3) thin base region, a thin (typically less than about 100 nm) collector depletion region, and a highly doped (typically more than about 10.sup.19 cm.sup.-3) collector contact region. Ballistic transport through the base region is possible, despite the high doping level, because the inelastic scattering rate can be relatively low in at least some highly doped compound semiconductors such as GaAs, AlGaAs, InGaAs, or InP. The elastic scattering rate in the base region can be relatively low if the dopant atoms have an appropriate non-random distribution. Techniques for achieving such a distribution are disclosed. Transistors according to the invention are expected to find advantageous use in applications that demand high speed, e.g., in repeaters in high capacity optical fiber transmission systems.

Abstract: In order to reduce parasitic capacitive cross-coupling in an integrated circuit, metallization lines in an array--for example, an array of word lines, of bit lines, or of bus interconnects--are geometrically arranged in a systematically progressive laterally (sidewise) marching sequence, whereby the identity of the lines located on either side of a given line keeps changing.

Abstract: A test circuit is described for measuring the specific contact resistivity r.sub.c of self-aligned electrodes contacting underlying diffused regions at a major surface of an underlying semiconductor wafer, as well as the sheet (lateral) resistance r.sub.s of the underlying diffused regions in some embodiments. The test circuit illustratively includes a pair of test MOS or other type of transistors advantageously made by a self-aligned metallization process simultaneously with the other MOS or other type of transistors to be tested. The two test transistors share a common diffused region, a self-aligned common controlled electrode contacting a diffused region underneath it, and a common control electrode. During test operation, both est transistors are kept ON by means of an applied above-threshold control voltage, while a current source forces current through one of the transistors.

Abstract: A hydrogen-free boron-containing membrane in tension exhibits advantageous properties for use as a mask in X-ray lithography.

Abstract: A CMOS logic circuit, such as a crossbar digital switch, multistage multiplexer logic tree in a two-column compact folded layout of two columns, each having a width equal to a single stage of the tree, in order to minimize wiring delays and hence signal skew. Each stage of the tree, except for the first, includes a symmetrized two-input CMOS NAND gate followed in cascade by a symmetrized CMOS INVERTER gate, to minimize signal skew otherwise caused by the difference between pull-up and pull-down gate delays of CMOS gates and the skew otherwise caused by variations in semiconductor manufacturing processing conditions and variations in ambient operating conditions (temperature and power supply voltages). Also, a detailed delay balancing scheme separately for pull-up and pull-down gate delays is implemented along a pair of signal paths for generating each output signal and its simultaneous complement without relative skew between them. In this way a single-chip 64 input.times.

Abstract: A squaring circuit (FIG. 1, 100; FIG. 3, 300) includes an operational amplifier (10) having its positive input terminal connected to ground, its negative input terminal connected through a nonlinear voltage-to-current conversion device (FIG. 1, T.sub.2, T.sub.3 ; FIG. 3, M.sub.1, M.sub.2, T.sub.2) to a balanced source of the input voltage (.+-.V.sub.IN), and its output terminal connected through a linear current-to-voltage conversion device (FIG. 1, R.sub.1 ; FIG. 3, T.sub.1, C.sub.1) to its negative input terminal. The circuit can be made to have a balanced output (FIGS. 2 and 5), and the circuit can be made in the configuration of either a continuous-time circuit (FIGS. 1 and 2) or a sampled-data circuit (FIGS. 3 and 5).

Abstract: Dislocation-free epitaxial layers on the surfaces of lattice mismatched single crystal substrates, such as germanium or gallium arsenide on silicon, can be grown provided the surfaces are suitably patterned, such as castellated or porous.

Abstract: A semiconductor memory circuit is arranged with an ordinary crosspoint row-column array of dynamic capacitor memory storage cells. Word serial content addressing is enabled by adding a separate combinational logic device, only one such device for each entire column bit line, typically comprising a comparator feeding a NAND gate to which masking data can be supplied.

Abstract: Integrated circuit chips with two (or more) multi-element logic paths--suffering from signal skew operation because of semiconductor processing variations--can be made to exhibit substantially reduced skew by designing the elements such that the sum of the pull-up delays in one logic path is approximately equal to the sum of the pull-up delays in the other logic path (or in each of the other logic paths) and such that the sum of all the delays (pull-down plus pull-up) in one path is substantially equal to the sum of all the delays in (each of) the other(s)--all in response to an input signal transition (low to high, high to low, or both) applied to each path.

Abstract: An interrupt controller circuit arrangement is used for encoding and storing "interrupt" signals indicating random (asynchronous) occurrence of corresponding events and for delivering corresponding "interrupt" (alarm command) signals to a (synchronous) microprocessor corresponding to the events as they occur. The events are divided into two (or more) sets in order to reduce the required number of latches and to increase the speed of operation. One (or more) of these sets consists of events which never can occur "simultaneously" (i.e., which are mutually exclusive in the sense that (within each of such sets) not more than a single one of the events can occur--and can occur only once--within a prescribed amount of time); the remaining set consists of the remaining events--i.e., those which can occur "simultaneously" or can occur simultaneously with one or more of those in the other set(s).

Abstract: A silicon semiconductor wafer containing a plurality of silicon integrated circuits formed therein or attached thereto contains at least one data bus to which some of the circuits are connected. Each of the circuits coupled to the data bus contains an arbitration request circuit which selectively passes a signal that requests that its circuit be given access to the data bus so it can transmit information to another circuit on the wafer. In addition, each of the circuits coupled to the data bus has an arbitration circuit which detects which of any of the circuits coupled to the data bus is requesting access to the data bus and facilitates its circuit gaining access to the data bus if its circuit has a higher preselected priority than any other circuit which is simultaneously seeking access to the data bus. The distribution of the arbitration request circuits and of the arbitration circuits simplifies layout and tends to improve the speed of operation.

Abstract: A differential operational amplifier circuit, having an input stage and an output stage, is balanced--i.e., is designed to have zero common mode component in its output--by means of a common mode feedback loop arrangement. This arrangement includes a common mode detector, connected for detecting the common mode signal component in a pair of outputs of the output stage of the circuit, and a pair of current steering devices, connected for drawing equal currents from each of the outputs of the input stage. During operation, the common mode detector feeds back a suitable control signal to each of the current steering devices, whereby the common mode component in the outputs is substantially completely suppressed.

Abstract: .[.A circuit for rotating a multibit binary word in either the right or the left direction includes a scale factor decoder receiving a scale factor word which specifies the magnitude of the rotation and a direction control signal which specifies the direction of rotation and providing a shift control word which is the same as the scale factor word when a right rotation is specified but providing a shift control word which is the complement of the scale factor word when a left rotation is specified. The circuit also includes a plurality of input buffers receiving an input word and providing corresponding input data, and a one-bit rotator receiving the input data and the direction control signal and rotating the input data in the right direction by one position when a left rotation is specified or providing the input data without rotation when a right rotation is specified.