Abstract: The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in the manufacture of semiconductor devices.

Abstract: A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a conductive spacer liner that effectively prevents the contact structure from being damaged during removal of the surrounding sacrificial contact medium material. The sacrificial contact medium is then replaced with a non-boron doped dielectric material.

Abstract: A solid source precursor material is delivered to a deposition chamber in vaporized form by utilizing a solid source precursor delivery system having either single or multiple stations(s) having a collection/delivery reservoir that is an intermediate stage between a solid source reservoir and a processing deposition chamber. Each collection/delivery reservoir transitions between a collection phase of the solid precursor and the delivery stage of the vaporized precursor during the deposition of a film.

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying the NMOS region is converted to a metal silicon nitride and the metal silicon compound overlying the PMOS region is converted to a metal silicide. NMOS transistor gate electrodes comprising metal silicon nitride and PMOS transistor gate electrodes comprising metal silicide can be formed.

Abstract: A flash memory comprising floating gate devices being connected to one-another through their source electrodes being self-aligned to their respective gate electrodes, a local tungsten interconnect making a substantially continuous connection to the sources.

Abstract: Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in the semiconductive substrate by being aligned to the first trench; and an insulation material substantially filling the first and second trenches. The isolation structure separates a non-continuous surface of a conductive region.

Abstract: Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal silicide. A transistor gate isolation capping layer is formed in the trench and on the metal silicide. Optional trench spacers can be added to reduce the critical dimension restraints of a given fabrication process and thus form a transistor having smaller feature sizes than the critical dimension.

Abstract: A structure and method for forming a magnetic memory having a number N of levels of magnetic memory cells by forming a plurality of levels of magnetic memory cells, each level including at least one magnetic memory core structure having first and second surfaces, forming a first access conductor connecting to the first surface, forming a second access conductor connecting to the second surface, wherein N+1 access conductors are formed per number N of levels of magnetic memory cells. The structure comprises a plurality of levels of magnetic memory cells, each level including at least one magnetic memory having a number N of levels of magnetic memory cells, including a magnetic memory core structure having first and second surfaces, the first and second surfaces each connecting to an individual access conductor, wherein N+1 access conductors are employed per number N of levels of magnetic memory cells.

Abstract: Methods to form contact openings and allow the formation of self-aligned contacts for use in the manufacture of semiconductor devices are described. During formation of a multi-layered resist, a hard mask material is introduced beneath an anti-reflective coating to be used as an etch stop layer. The multi-layered resist is patterned and etched, to transfer the desired contact pattern to a substrate material, such as a silicon substrate, to form contact openings therein. The contact openings provide for the formation of self-aligned contacts therein.

Abstract: A storage capacitor plate for a semiconductor assembly having a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent the conductive material, a capacitor cell dielectric overlying the silicon nanocrystals and an overlying conductive top plate. The conductive storage plate is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, wherein silicon nanocrystals contain conductive impurities and are adjoined to form a substantially continuous porous conductive layer.

Abstract: An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing an the presence of ultraviolet light and ozone gas, an ambient containing ozone gas or an ambient containing an NF3/ozone gas mixture.

Abstract: A simple trip-wire or magnetic circuit associated with a shipping container provides continuity, which is detected electrically. Simply, if continuity is disabled by a forced entry of the container, electrical detection means, such as a radio-frequency-identification (RFID) tag, will alert the owner or monitoring station. The trip-wire concept would require the replacing of a broken trip wire (resulting from forced entry), while the magnetic circuit concept can be reused repetitively. In a second embodiment a magnetic circuit and the detection device (RFID tag) are embedded into the shipping article during manufacturing. The preferred detection device, an RFID tag, could also be a battery backed transceiver type on which a replaceable or rechargeable battery could be mounted on the inside of the shipping container during manufacturing. The RFID tag would communicate with an interrogator unit, which could be connected to a host computer.

Abstract: A simple trip-wire or magnetic circuit associated with a shipping container provides continuity, which is detected electrically. Simply, if continuity is disabled by a forced entry of the container, electrical detection means, such as a radio-frequency-identification (RFID) tag, will alert the owner or monitoring station. The trip-wire concept would require the replacing of a broken trip wire (resulting from forced entry), while the magnetic circuit concept can be reused repetitively. In a second embodiment, a magnetic circuit and the detection device (RFID tag) are embedded into the shipping article during manufacturing. The preferred detection device, an RFID tag, could also be a battery backed transceiver type on which a replaceable or rechargeable battery could be mounted on the inside of the shipping container during manufacturing. The RFID tag would communicate with an interrogator unit, which could be connected to a host computer.

Abstract: The present invention develops an opaque or translucent glass film for use in semiconductor fabrication processes, such as in EPROMs or radio frequency integrated circuits. The opaque or translucent film is developed by forming an glass layer while and introducing a light blocking pigment into the glass layer. The light blocking pigment is made up of a metal oxide, such as titanium oxide (TiO.sub.2), an organic dye, bone ash, or dispersed metal particles. The glass layer is made up of spin on glass.

Abstract: A method for compensating against wafer edge heat loss during rapid thermal processing includes a semiconductor wafer that is exposed to uniform radiant energy across the entire wafer surface. The wafer is exposed by projecting a radiant energy image onto the edge of said semiconductor wafer while providing radiant energy rays directly to the wafer's surface. The radiant energy image comprises reflecting radiant energy rays that pass through a positionally adjustable object onto the edge of the wafer. The positionally adjustable object is optional and is mounted between an optical lens and a radiant energy source or is mounted between a reflector and each radiant energy source (A second optical lens is optional). The energy rays absorbed at the edge of the wafer contain more heat intensity than do the rays which are absorbed by the inner portion of the wafer, thus producing uniform heat across the entire wafer.

Abstract: The present invention teaches a method for etching a tungsten silicide (WSi.sub.x) film overlying a polysilicon film in an enclosed chamber during a semiconductor fabrication process, by the steps of: providing a patterned mask overlying the WSi.sub.x film thereby providing exposed portions of the WSi.sub.x film; presenting an etchant chemistry comprising NF.sub.3 and HeO.sub.2 to the exposed portions of the WSi.sub.x film at a temperature ranging from -20.degree. C. to 100.degree. C., thereby etching away the exposed portions of the WSi.sub.x film and simultaneously etching substantially vertical sidewalls in the WSi.sub.x film, the etching continues into the polysilicon film, thereby forming a WSi.sub.x /polysilicon stack having substantially vertical sidewalls.

Abstract: The present invention teaches a method for fabricating semiconductors. The method initially comprises the step of forming a conformal layer superjacent at least two conductive layers. The conformal layer preferably comprises tetraethylorthosilicate ("TEOS") and has a thickness of at least 50 .ANG.. Subsequently, a barrier layer is formed superjacent the conformal layer to prevent subsequent layers from diffusing into active regions. The barrier layer preferably comprises Si.sub.3 N.sub.4, though other suitable materials known to one of ordinary skill in the art may be employed. Further, a glass layer is then formed superjacent the barrier layer. The glass layer comprises at least one of SiO.sub.2, phosphosilicate glass, borosilicate glass, and borophosphosilicate glass, and has a thickness of at least 1 k.ANG.. Upon forming the glass layer, the glass layer is heated to a temperature of at least 800.degree. C. for at least 15 minutes while introducing H.sub.2 and O.sub.

Abstract: The present invention is a process for forming diffusion areas and field isolation regions on a silicon substrate, by the steps of: growing a field oxide layer on the surface of the substrate; forming a mask pattern which exposes a plurality of spaced-apart regions on the surface of the field oxide layer; removing portions of the field oxide layer in the exposed, spaced-apart regions with an anisotropic etch so as to leave a cavity in each spaced-apart region, each cavity having as its floor an exposed region of the silicon substrate, and having vertical walls of field oxide; angularly chamfering the rim of each cavity with a facet etch; and filling each cavity with silicon using selective epitaxial growth, and using the floor of each cavity as the seed crystal for such growth.

Abstract: An embodiment of the present invention provides a method to reduce a regulated power source voltage spike during operation of a dynamic random access memory by the steps of: providing a voltage spike reducer enabling pulse via a pulse generator circuit responsive to a pulse generator input signal; translating the voltage level of an unregulated power source via a level translation stage during the presence of the voltage spike reducer enabling pulse; amplifying a translated voltage level; and providing a measure of current from the unregulated power supply to the regulated power supply via a current driver stage that is responsive to the amplified translated voltage level translation.

Abstract: The present invention teaches a method for reducing sheet resistance in the fabrication of semiconductor wafers. A silicon substrate having a gate oxide layer thereon is provided in a chamber. Subsequently, a polysilicon layer is formed superjacent the gate oxide layer in situ by exposing the silicon substrate to a first gas comprising at least one of silane, disilane, and dichlorosilane, and radiant energy at a temperature substantially within the range of 500.degree. C. to 1250.degree. C. for at least 10 seconds. The polysilicon substrate can be doped with a material such as phosphorus, arsenic and boron for example, by exposing the polysilicon to a second gas under the stated conditions. A conductive layer comprising at least one of tungsten silicide (WSi.sub.x) and titanium silicide (TiSi.sub.x) can be formed superjacent the polysilicon by exposing the polysilicon to a third gas comprising at least one of WF.sub.6, TMAT and TiCl.sub.4.