Abstract: Methods and apparatus for cache flush control and write re-ordering in a data storage system are provided. A cache flush control method includes cache flushing information stored in a cache memory to a first storage apparatus of a plurality of storage apparatuses included in a data storage system when a cache flush condition is generated, and performing a write command in a second storage apparatus of the plurality of storage apparatuses which has a write speed lower than the first storage apparatus according to information stored in the first storage apparatus processed with the cache flush.

Abstract: A voice coil motor (VCM) is controlled by applying a bipolar square wave actuator current to the VCM and calibrating a back electromotive force (back-EMF) measurement on the VCM in response to the square wave actuator current. Back-EMF on the VCM is measured while an actuator arm coupled to the VCM is in motion, and the VCM is controlled to move the actuator arm in response to the measured back-EMF voltage.

Abstract: In general, this disclosure describes techniques for implementing a system-wide reset of multiple devices. The techniques ensure that when any one of the devices of the system is reset, all the devices are reset. For example, a system includes a master reset device and a plurality of slave reset devices that are interconnected by a single reset line to provide improved robustness against electrostatic discharge (ESD) and electromagnetic pulse events. The master reset device detects a reset signal on the reset line and retransmits a true reset signal on the reset line in response to detecting the reset signal. Additionally, the master reset device may enter a blocking state after retransmitting the true reset signal to prevent detecting the reset signal that it transmitted on the reset line to avoid reset lockup.

Abstract: A serial ATA interface calibrates serially connected components of a computer system linked by the interface to a negotiated data transmission speed. The interface negotiates the fastest data transmission speed supported by the serially connected components. Link parameters associated with the negotiated data transmission speed are calibrated and implemented in a Phy layer of the interface before data is transmitted across the interface. The calibrated link parameters include signal transmission settings for amplitude, pre-emphasis, equalization and timing. Default settings of the link parameters correspond to the slowest data transmission speed supported by the serially connected components. The serially connected components are calibrated each time system power is initialized. The serially connected components can be a host computer linked to a data storage device such as a backplane-based storage subsystem.

Abstract: A circuit for regulating voltage in a power driver, the circuit comprising a current amplifier adapted to measure current flowing through an input resistor, separate AC and DC components of the current flowing through an input resistor, and apply an AC gain factor to the AC component and a DC gain factor to the DC component.

Abstract: A storage device responds to a content request by watermarking the content and providing the watermarked content to the requester. The watermarked content uniquely identifies the storage device so that the storage device is traceable from the watermarked content.

Abstract: A filter representing a complex impedance of a motor system based on a deviation between a first voltage driven by a command signal and a second voltage driven by the command signal can be dynamically adjusted. The motor system can be held in a steady state, eliminating back electromotive force, by providing zero mean current excitation.

Abstract: Examples of the present invention relate to reduction in acoustic noise by tuning seek characteristics of a servo controller, depending on a radial position of a head relative to a disk. The servo controller can provide compensation for acoustic resonance modes.

Abstract: A method of identifying a string or chain of efficient or “good enough” disc operations for processing (a pseudo optimal chain) is provided. A “pseudo optimal chain” comprises a string or chain of operations that, while not necessarily the optimal string or chain, provides an efficient sequence of operations that can be determined by comparing individual operations to predetermined selection criteria. In contrast to a true optimization technique that can require computing up to N! combinations for N operations, the string or chain of efficient or “good enough” disc operations allows for relatively simpler computations.

Abstract: A RAID system is provided which can be implemented as a hardware RAID system while avoiding certain shortcomings of previous RAID systems. The RAID system makes it possible to avoid or reduce the number of buffers or processors and can take advantage of drive logic to achieve RAID functions or enhancements. RAID functionality can be provided in a manner to accommodate one or more ATA drive interfaces. To avoid drive replacement problems, host requests for drive serial numbers are responded to with a mirror serial number. In one embodiment, the read address is used to select which drive will perform a read operation.

Abstract: In a particular embodiment, a system is disclosed that includes a solid-state data storage medium, a disc data storage medium, and a controller adapted to selectively adjust a spindle speed associated with the disc data storage medium and a buffer size associated with the solid-state data storage medium responsive to a trigger.

Abstract: According to one embodiment of the present invention, a data storage device comprises a generic host interface and a media controller. The host interface has a channel select bit encoder to assert one or more channel select bits to be decoded by the media controller to indicate one or more virtual channels through which the host interface will communicate with the media controller over a data bus. A virtual channel controller in the host interface establishes a peer-to-peer connection with a virtual channel controller in the media controller based on the virtual channel indicated by the one or more channel select bits. A communication controller in the host interface implements a communication protocol for communication with a host and transfers data to and from the media controller via the peer-to-peer connection based on the communication with the host.

Abstract: Methods and structures for mapping of logical to physical block addresses within a disk drive to provide independence of the logical block size and the physical disk block size. The independence of the logical and physical block sizes enables numerous beneficial features to improve disk drive capacity, performance and reliability. In one exemplary aspect, indirect mapping table structures and methods map an LBA to an associated IBA representing a block of the same size as the logical block. The IBA is then converted to a corresponding starting quantum unit of data identified by a QA. The QA is, in turn, converted to a disk block identified by a starting DBA and an offset within that DBA. The disk block may be of variable size and is independent of the size of the identified LBA. Numerous other features are enabled by the logical to physical mapping features hereof.

Abstract: Methods for writing servo fields on a rotatable data storage disk using reference patterns on the data storage disk include generating a clock signal, reading a reference pattern signal from a surface of the disk, generating a phase error signal in response to a phase offset between the clock signal and the reference pattern signal, subtracting a timing control value from the phase error to provide an adjusted phase error, generating a frequency control signal in response to the adjusted phase error, and adjusting the frequency of the clock signal. The timing control value is generated in response to the phase error signal and the frequency control signal.

Abstract: A clamping circuit is included in a phased motor control circuit, particularly on an electrical connection connected to at least one electrostatic discharge cell and/or the driver control electronics of the phased motor control circuit. The clamping circuit triggers when a voltage that exceeds a clamping turn-on threshold occurs on the electrical connector, sourcing or sinking the discharge current so as to protect the electrostatic discharge cells and/or driver control electronics from destruction by said discharge current.

Abstract: In a servo control loop, phase detection between a clock signal and servo burst fields on a movable storage media is carried out with compensation for phase error and frequency error in the timing of servo burst fields.

Abstract: An electronic device includes a flag circuit configured to generate a status flag indicating whether or not a power supply voltage to the electronic device has been cycled, and a controller configured to control an operation of the electronic device and to modify an operational characteristic of the electronic device in response to the status flag indicating that the power supply voltage to the electronic device has been cycled. Methods of operating an electronic device include generating a status flag indicating whether or not a power supply voltage to the electronic device has been cycled within about a defined time, and modifying an operational characteristic of the electronic device in response to the status flag indicating that the power supply voltage to the electronic device has been cycled within about the defined time.

Abstract: Extracting transducer position information from bit patterned magnetic media includes providing a magnetic storage medium having at least one data array with multiple discrete and separated recording bits and providing the transducer adjacent the data array. A readback signal dependent upon the multiple recording bits is generated with the transducer. Determining the transducer position information further includes generating at least a first position signal and a second position signal from the readback signal.

Abstract: Various embodiments relate to selectively inhibiting output from a transducer in response to the rate of change of acceleration that is experienced by the transducer. The rate of change of an acceleration signal, which is indicative of transducer's acceleration, is detected. Output of a signal through the transducer is selectively inhibited in response to the detected rate of change of the acceleration signal. A related apparatus can include a circuit that detects the rate of change of an acceleration signal and generates a transducer output inhibit signal in response to the detected rate of change of the acceleration signal. The transducer writes data on a recordable media. The accelerometer generates an acceleration signal that is indicative of transducer vibration. The circuit selectively inhibits writing of data through the transducer in response to a rate of change of the acceleration signal.

Abstract: An embodiment of a method for compressing data includes variable length coding one or more values of control codes generated from dictionary coding the data, wherein the control codes comprise literals and indices, wherein each index comprises a length value and a pointer to previously read in data. An embodiment of a system for losslessly compressing input data includes a modeler operable to determine whether a set of input data matches prior input data, an encoder operable to generate control codes including one or more literal control codes and one or more index control codes, wherein each index control code includes a pointer to a location in the input data and a length value indicating a number of bytes to copy from the location, and wherein the length value is variable length coded.