Abstract: A bus signal detector for a signal transmitted via a bus (12) has an edge detector (14) which supplies a signal (S.sub.F1) indicating the occurrence of a signal edge (F1) when the voltage on the bus (12) suddenly changes by at least a predetermined relative threshold (.DELTA.U.sub.s) in relation to a reference voltage (V.sub.ref) continuously adapted to the quiescent voltage of the bus (.sub.12). An evaluating circuit following the edge detector (14) uses the signal (S.sub.F1) supplied by the edge detector (14) to produce an output signal indicating a bus signal.

Abstract: An edge detector for producing output signals in a manner dependent on positive and/or negative edges of an input signal comprises a control circuit (10), by which a reference signal level (V.sub.ref) available at a storage element (C) may be continuously assimilated at a predeterminable first level change rate (PG.sub.1) to the input voltage level (V.sub.E). It moreover includes at least one comparison circuit (12), which supplies an output signal (V.sub.A, V.sub.A ') indicative of the occurrence of an edge, when the input voltage level (V.sub.E) changes by at least a predeterminable relative threshold value (U.sub.off) in relation to the reference voltage level (V.sub.ref). The control circuit (10) comprises a delay means (14) whose delay time (.DELTA.t.sub.D) causing a delay in the assimilation of the reference voltage level is selected to be equal to the ratio of the predeterminable relative threshold value (U.sub.off) to the predeterminable first level change rate (PG.sub.1).

Abstract: This invention relates to an improved program counter which is capable of both incrementing the program count as well as decrementing the program count. This functionality provides improve implementation of decision trees in computer logic. The value of an integer is determined and compared to a predetermined constant. For each of, for example, three conditions a different decision is made. One of those decisions enables the program counter to continue on the current program list. A second decision moves the counter to a new list and causes decremental movement of the counter. The final decision enables movement to the same location as the second decision but causes incremental movement of the counter.

Abstract: A edge detector for the production of output signal in a manner dependent on positive and negative edges of a square wave signal comprises a differential amplifier with two base-coupled transistors (Q1, Q2). Each emitter of such transistors is connected via a constant current source (S1 and, respectively, S2) with a supply voltage line (10) and the emitter currents of the transistors are split up between two collectors, of which the first ones are connected with one another and, via a third constant current source (S3), with ground (12). Two output loops each comprise a series circuit composed of a resistor (R3, R4) and the collector-emitter path of an output transistor (Q3, Q4) between ground (12) and the supply voltage line (10). In the case of each of such output transistors (Q3, Q4) the base is connected in each case with a second collector of the base-coupled transistor (Q1, Q2) so that the switching state of the output transistors (Q1, Q2) is set by the voltage at each second collector.

Abstract: A semiconductor wafer and semiconductor device manufactured from the wafer. The wafer has a conductive layer 33A intermittently formed in the longitudinal direction of a scribe area 2. The conductive layer's width shorter width than its length and shaped so that the scribe area is cut in the longtitudinal direction including the location of said width. The invention provides a semiconductor wafer not giving rise to faults, such as short-circuiting due to shavings, and not requiring any modification in the scribed width, blade width, or pad size when sawing conductive layers in the scribe area, such as the above-mentioned pads of the TEG.

Abstract: An MLR (multilayer resist) 3 is formed on a BPSG layer 2 on top of a silicon wafer 1, then dry etched using an etching gas 8 to form a contact hole 2a on the BPSG layer 2. Next, the polymer residues 9a and 9b adhering to the side walls of the contact hole 2a and the surface of the BPSG layer 2 are subjected to a cleaning treatment using a cleaning treating liquid that contains 0.04-0.12 wt % hydrogen fluoride, thereby removing the polymer residues 9a and 9b.During etching the presence of the polymer residue layer 9 prevents etching in the horizontal direction, thereby allowing the formation of a highly precise contact hole 2a. In addition, because the treating liquid has the composition described above, the aforementioned polymer residues 9a and 9b are removed, thereby avoiding any degradation of the electrical characteristics. In addition, corrosion of the side walls of the contact hole due to the cleaning treating liquid is prevented, thereby maintaining the high level of contact hole precision.

Abstract: A drive circuit in which the rise and fall characteristics with multiple voltages are made the same, while maintaining a high breakdown voltage. Drive circuit 70, which supplies power supply voltages VH and VL and voltage VM intermediate between them to output pad 32, is composed of p-channel MOS transistor P5 and n-channel MOS transistors N5, N6 and N7. When the output voltage changes from VH to VM, both transistors N6 and N7 conduct, and when the output voltage changes from VL to VM, only transistor N6 conducts. The transistors that supply intermediate voltage VM are constructed of transistors of the same conductivity type, so that the rise and fall characteristics to VM can be made the same while the breakdown voltage of the transistors in the circuit that supplies this intermediate voltage VM is kept high.

Abstract: A bus driver circuit having a driver input (16) for the reception of a data signal and a driver output (20) for the application of the output voltage of a voltage source (Vcc) to a bus core (10) in a manner dependent on the presence of a data signal at the driver input (16). It possesses a first controllable switch (A) placed between the voltage source (Vcc) and the driver output (20) and a control circuit loop (B), which on the application of the data signal to the driver input (16) is able to be placed in an active state by its producing a drive signal putting the controllable switch (A) in a conducting state. A second controllable switch (C) is between the control circuit loop (B) and the driver input (16). A comparator (D) compares the voltage at the driver output (20) with a reference voltage (V.sub.

Abstract: A method for making ferroelectric thin film form capacitors that maintains the insulating characteristics of the thin film capacitors formed on the semiconductor devices while reducing the leakage current and ensuring a yield sufficient for applications to ULSIs such as DRAMs. A metal or oxide thereof, which contains structural elements of a metal forming the ferroelectric thin film, is formed as islands in the initial stage of formation or during the formation of a ferroelectric thin film in semiconductor devices. This suppresses the formation of columnar crystals.

Abstract: The present invention relates to a supply battery arrangement having 3 terminals, for example a battery for a video camera recorder. This arrangement permits employing the battery both as an intelligent battery and as a non-intelligent battery capable of operating normally on devices of the standard video camera recorder type and also capable of communicating with a equipment or an intelligent device and displaying the state of charge with no additional terminals. The battery arrangement comprises a negative terminal (24) and a positive terminal (22) for supplying the equipment or the device with a voltage coming from the battery, a universal "T" terminal (26) operating as a thermal measuring means and a data terminal or a charge control output when it is employed by a computer, a charger or some other intelligent equipment or device.

Abstract: A semiconductor device with a force and/or acceleration sensor (12), which has a spring-mass system (14, 16) responsive to the respective quantity to be measured and whose mass (16) bears via at least one resilient support element (14) on a semiconductor substrate (20). The semiconductor substrate (20) and the spring-mass system (14, 16) are integral components of a monocrystalline semiconductor crystal (10) with a IC-compatible structure. The three-dimensional structural form of the spring-mass system (12) is produced by anisotropic semiconductor etching, defined P/N junctions of the semiconductor layer arrangement functioning as etch stop means in order to more particularly create a gap (22) permitting respective movement of the mass (16) between the mass (16) and the semiconductor substrate (20).

Abstract: Battery pack arrangement having a control module 305 in the form of a programmed microcontroller and associated components on a printed circuit board, one or more battery cells 21 in which the respective cells are interconnected by metal conductive straps 22, wherein one of the interconnecting straps has a portion 309 of reduced width so as to serve as a current sensing element in conjunction with the control module 305. The reduced width of the interconnecting conductive strap 22 provides increased electrical resistance to the current flowing therein, with the value of the current sensing element 309 being measurable and storable in memory. The microcontroller and a regulating component of the control module are arranged to be located in intercellular space between successive cells in the cell array 21.

Abstract: A voltage generating circuit for providing a prescribed voltage, such as 1/2V.sub.DD of the power source voltage V.sub.DD, wherein the capacity of the current and the response time of the voltage generating circuit is significantly improved. When the output voltage V.sub.OUT of the voltage generating circuit drops suddenly from a reference value 1/2V.sub.DD and goes below the lower limit of an allowable voltage level VM-, an n-type MOS transistor MN5A of an output voltage detecting circuit 14 turns on. The potential of the gate terminal for a p-type MOS transistor MP6A in a digital output circuit 16 is pulled to the level of the output voltage V.sub.OUT via the transistor MN5A that was turned on, and said p-type MOS transistor MP6A is turned on in the saturated area more or less perfectly.

Abstract: A noise-reducing circuit for performing effective noise reduction without an accompanying trailing phenomenon or other adverse effects with respect to the edge of a moving image portion. Digital sample values as output from an A/D converter are input to a waveform equalizer, which performs prescribed waveform equalizing processing with a MUSE format resample condition being met. In a noise reducing unit, for the various resample values from waveform equalizer, the correlation value in the impulse response waveforms corresponding to the resample values is derived from the sample values around the resample value and the other resample values, and the sum of the resample value and the correlation value is calculated. In this way, a resample value with an increased signal/noise ratio can be obtained at the output terminal of the noise reducing unit.

Abstract: A method and apparatus for forming a synthesized optical image with all of the desired objects in focus. A prescribed number of optical images of the same scene are provided by recording an optical image at a respective focal distance and changing the focal distance for each additional optical image as recorded. The optical images are subjected to wavelet transformation to form a multi-resolution representation. The coefficients of the various multi-resolution representations are compared at the same position to detect the maximum spectral amplitudes. Based on the detected maximum spectral amplitudes, another multi-resolution representation is obtained. Then, an inverse wavelet transformation is performed to obtain the synthesized optical image.

Abstract: A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.

Abstract: An arbiter circuit for determining priority as between two or more competing request signals and applicable for use in a memory system having a number of memories operating independently without interfering with one another. For each of a number of memories, a receiving circuit 10(i) and an arbitration circuit 12(i) with standardized configurations are allotted. Common memory cycle clock pulse ARB-CLK is sent from memory cycle generator 16 to all of arbiter units 14(1)-14(N) . From the arbiter units 14(1)-14(N) , the commands for the respective memories are output in synchronization to each other based on memory cycle clock pulse ARB-CLK.

Abstract: An automatic wiring device for deriving the shortest distance wiring route in a short time, in designing a semiconductor integrated circuit. First, based on the coordinate positions of respective signal terminals and the coordinate positions of respective channel wiring areas of respective lines, the X-coordinate positions of all of the partial wiring routes ay1, ay2 . . . , by1, by2 . . . , ayr2, byr2, ayr3, byr3 extending in the Y-direction are determined. Then, based on the positional relations among respective partial wiring routes extending in the Y-direction in respective interlinear wiring areas, the Y-coordinate positions of all of the partial wiring routes ax1-2-3, bx1-2-3, axr2-4-r3, bxr2-r3, axr3-5-6, bxr3-3-4 extending in the X-direction are determined. By these determinations, the wiring routes WA, WB for connecting the signal terminals of respective groups, in a network form, with the shortest distance, are determined.

Abstract: A pile product comprising a plurality of relatively long, thin face fibers extending from a base is molded from a crosslinkable polymeric material. During formation of the fibers, crosslinking of the polymeric material is initiated by heat activating a substance incorporated in the polymeric material which promotes crosslinking. Crosslinking imparts hot strength to the pile fibers so that the pile product, while still hot, can be removed from the mold without materially deforming the fibers. Consequently, the time it takes to mold the pile product is significantly reduced, thereby increasing productivity and lowering the cost of the product. Moreover energy is conserved because the mold is not continuously cycled between high and low extremes in temperature.

Abstract: An abradable seal material suitable for high temperature application in turbomachinery comprising a sintered mat of (1) randomly disposed fine metal fibers, or (2) fine metal powders or (3) both fibers and powders. The metal fiber and powder are composed of an alloy consisting essentially of I, Al, Cr, II, or I, Al, Cr, III, wherein I is at least one member of the group Fe, Co, Ni, and Co plus Ni, II is a member of the group consisting of Y, Sc and Rare Earths, and III is at least one member of the group consisting of Si, Hf, Zr, Cb, and Ta. The exposed surfaces of the fibers and powder forming the seal are protected against oxidation at high temperatures by a coating of Al.sub.2 O.sub.3 which is formed on the substrate. Said substrate has an Al content of at least 4% to replace spalled Al.sub.2 O.sub.3 and for "healing" any Al.sub.2 O.sub.3 scale fractures.