Abstract: A cache memory for use between a processing unit and a main memory includes a prefetch buffer, a use buffer, and a head buffer. The prefetched buffer is a FIFO or LRU register which prefetches instructions from contiguous memory locations after the address specified by the program counter. The head buffer is a FIFO or LRU register which is utilized to store instructions from the tops of the program blocks which are accessed from main memory following recent cache misses. The use buffer is a relatively large, inexpensive buffer, preferably a directly mapped buffer, which stores recent hits from the prefetched buffer as well as selected instructions from main memory following cache misses.

Abstract: A multistation communication bus system including a plurality of master stations and a slave station for transmitting information from the master stations and slave station using a frame based arbitration process. The master station which wins the arbitration transmits a framewise organized message including locking and unlocking signals for respectively, locking and unlocking an addressed slave station, thus blocking any other master station from accessing the slave station for a duration of multiple frames of the message.Any other master station, upon detecting this blocking condition, executes a first sequence of retry undertakings at a combined time length that is substantially less than a standard maximum value of the duration. A second sequence of less frequent retry undertakings at a combined time length that is more than a standard maximum value of the duration may then be attempted.

Abstract: A counter and/or divider arrangement, comprising at least two subsidiary counter circuits, each of which comprises a number of flipflops which are concatenated in respect of their data inputs and outputs, all subsidiary counter circuits receiving a common clock signal, and also comprising at least one logic element, enables the implementation of arbitrary counting operations or division ratios with a low expenditure as regards circuitry and with low-noise operation in that in each logic element signals from the data output of one of the flipflops of at least a part of the subsidiary counter circuits are combined in conformity with an AND-function so as to form an associated resultant signal, each of the resultant signals being applied to at least one of the subsidiary counter circuits as a reset signal in order to switch the subsidiary circuit to an initial state, an output signal being formed from at least one of the resultant signals, the product of the total numbers of flipflops of all subsidiary counter c

Abstract: A graphical tablet and a stylus interact electromagnetically with one another. The stylus includes a coil and a transducer to affect an inductance of the coil in response to a force exerted on a tip of the stylus. The transducer comprises first and second ferrite cores. The cores are mounted to move with respect to one another in response to the force. The cores are substantially in contact with one another in the absence of the force. Disengaging causes a well detectable jump in the inductance.

Abstract: The invention relates to a norms computation procedure applied within a neuronal network structure or a computer. It permits determination of the norm of the new synaptic coefficients without necessitating their explicit computation. To this end, the structure comprises a processing unit 10 which determines output potentials y.sub.k and variation .DELTA..sub.k, a storage unit 13 for the old and new norms and a computational unit 15 for the new norms. The latter are thus rapidly determined without needing to call the synaptic coefficients in memory. The procedure can be utilized with certain algorithms which necessitate a computation of norms.

Abstract: An integrated services communication system ISDN in which a plurality of ISDN supported terminal stations can be coupled to an S.sub.0 bus coupled to a private branch exchange, of which a maximum of 2 terminal stations can be active over B-channels. Them is proposed also to connect incompletely ISDN supported terminal stations to the S.sub.0 bus, which stations have many non-ISDN supported features, there being investigated on line cards which type of terminal station is connected. On the basis of a Terminal Endpoint Identifier (TEI) in a layer-2 message, either a standard ISDN protocol is handled from layer-2 onwards, or a firm-owned protocol.

Abstract: Telecommunication systems such as PABXs are known which comprise ISDN digital linecards with a number of ISDN basic access interfaces. A telecommunication device is proposed comprising configurable ISDN digital linecards. To this end the linecards are provided with configuration means for independently configuring each ISDN basic access interface with respect to the other ISDN basic access interfaces as to mode setting and phantom power feeding to the transmission line to be coupled to the interface. The modes to be set are ISDN-NT or ISDN-TE mode. It is achieved that the PABX can be set to customer specifications without customer specific linecards having to be manufactured. Accordingly, no high manufacturing change-over costs are involved and no expensive extra documentation sets have to be drawn up, as would have been the case when many customer specific linecards would have to be manufactured.

Abstract: The system generates a composite image on a pixel-by-pixel basis by selectively mapping source pixels provided by video sources of different video formats onto destination pixels in the composite image. The mapping is accomplished by encoding the source pixels into digital words, each word having a color information part and a video format identifier, used to decode the color information part upon processing to organize the composite image. Combining video signals with computer-generated graphics data is achieved under control of the graphics data being interpreted either as video format identifier or as color. If the color of the destination pixel is determined by one of the video sources, the graphics data is used to select the appropriate decoding. The system permits a modular architecture and simple merging with a PC.

Abstract: At least a first and a second digital signal, both in parallel form, are converted to a single serial signal and transmitted from a digital color decoder to a signal processing unit so as to avoid picture disturbances in the signal processing unit. The first digital signal is dependent on the instantaneous value of a clock frequency used in the decoder for processing a digital color picture signal, and the second digital signal is dependent on the instantaneous value of a chrominance subcarrier frequency generated in the decoder and used for color decoding.

Abstract: A non-volatile memory cell and array of such cells is provided. The memory cell includes a single transistor floating gate cell fabricated on a sidewall of a silicon pillar etched into a silicon substrate. The memory cells are arranged in an array of rows extending in a bit line direction and columns extending in a word line direction. A substantially smaller cell and array size is realized by limiting the dimension of the pillar and the bit line in the word line direction to be the minimum line width as limited by the lithography.

Abstract: A device for generating multi-directional commands, comprising at least one plate provided with strain gauges (R.sub.1 -R.sub.4) (R.sub.5 -R.sub.8) which detect the multi-directional deformations incurred by the plate under the influence of a force F exerted on a surface of the plate. One of the extremities of the plate cooperates with a support and the plate bears, by way of its other surface, on a fulcrum at the other extremity. The fulcrum may be formed by the head of a microswitch, the extremity of the plate being linked to the support. The microswitch is capable of controlling operations for the activation of the device and/or the validation of the electric signals from the strain gauges. The orientation of the force F with respect to the axis of the fulcrum enables the issue of multi-directional commands. The device has a shape ergonomically adapted to handling by means of a single hand.

Abstract: Arithmetic unit for multiplying long integers modulo M and R.S.A. converter provided with such multiplication device.A systolized and modular arithmetic device has a control module, followed by a series arrangement of processing module, followed by a tail module. For multiplying an integer P and an integer Q modulo a third integer M, a provisional product is incremented each time with Q for a -1- bit in P, preceding by a doubling of the product. For a -0- bit only the doubling ensues. Normalizing mod M is effected by adding the complement of M, W, under control of propagated carry values. A similar procedure is proposed for exponentiation of Q. F.

Abstract: A television receiver includes a teletext decoder which is adapted to check whether a keyword entered by the user occurs in a teletext cycle. The teletext pages with the searched keyword, or their page numbers, are identified and stored for later display or selection. The receiver has arrow keys for selecting the keyword on the display screen so that an alphabetical keyboard is not necessary. The receiver also includes a non-volatile memory in which a personal index of keywords can be programmed.

Abstract: The invention describes the organizing and accessing of data pertaining to an engineering process. The process is partitioned into subprocess which are linked in a directed-acyclic-graph. Each link has a source node and a destination node, indicating which source node(s) must have been executed to provide the data necessary for executing the destination nodes. Executing any subprocess provides an instance of data associated to that node. The latter instances are linked in a second directed-acyclic-graph wherein each link indicates that part or all of the data at the source node has effectively been used for generating the data at its destination node. The two graphs are interlinked and provide for easy browsing of the data as well as for easy selection of input data for engineering subprocesses.

Abstract: A magnetic position sensor system including a magnetic medium divided into a plurality of areas of magnetization for producing a magnetic field with a variable intensity. The magnetic medium includes a first side, a second side and a longitudinal axis. A Hall cell is used for detecting the intensity of the magnetic field produced by the magnetic medium and for producing an electric signal which corresponds to the intensity detected. The magnetic medium is movable with respect to the Hall cell so that the Hall cell scans along the first side of the medium along the longitudinal axis and detects the intensity of the magnetic field at any given point along the longitudinal axis of the medium.

Abstract: A multipage teletext decoder is to capture, store and refresh a plurality of teletext pages as rapidly as possible. The number of acquisition circuits for this purpose is limited so that a subsequent request number is applied as rapidly as possible to each acquisition circuit after a page has been received. However, the corresponding page may already have passed. To avoid this, the number of the next capturable page is calculated. Of the request numbers the number which is as close as possible is selected.

Abstract: A television receiver including a teletext decoder is adapted to continue the further acquisition of a page in another memory after said page has been received. After each reception of the page it is checked whether this page has already been previously received and stored with the same sub-code. If this is not the case, the acquisition is continued in a further memory so that all sub-pages of a rotating page are stored without the user's intervention being required and without the displayed page rotating. If the sub-page has already been previously stored, the acquisition is continued in the previously written memory. If the sub-page is a displayed sub-page, it is replaced by the new version.

Abstract: The invention relates to a multilayer printed circuit board, in particular, for high-frequency operation, having least an outer, plane dielectric layer for accommodating interconnection paths of equal cross-section and component as well as further alternately provided metallic and dielectric layers for forming a reference earth and for the voltage supply to said interconnection paths and components via plated-through holes.

Abstract: Method of electronic payment by chip card.According to the invention, each token carries a number making it possible to check its authenticity.The invention is used for electronic payment.

Abstract: Method for compiling program instructions to reduce instruction cache misses and instruction cache pollution. The program is analyzed for instructions which result in a non-sequential transfer of control in the program. The presence of branch instructions and program loops are identified and analyzed. The instructions are placed in lines, and the lines are placed in a sequence to minimize potential misses.