Abstract: A method, system and apparatus for providing inter-connective access of a plurality of controllers to a plurality of serial storage devices are provided. Serial storage devices are provided with a serial operative connection to a data communication bridge. The bridge is operatively coupled to a plurality of controllers. The plurality of controllers is provided concurrent targeted connections to the set of serial storage devices. In one embodiment, InfiniBand® technology further increases the scalability and enhances the reliability of a data communication system provided with a plurality of (S-ATA) storage devices. The reliability of the data communication system is enhanced because if one controller should fail, another controller may still achieve and maintain access to the plurality of serial storage devices.

Abstract: A table for identifying potentially bad location addresses based on prior knowledge and performing specific operations using the table data to ensure write recovery is disclosed. A Write Recovery Table (WRT) is provided, which consists of a list of LBAs requiring such special write recovery action so that a WRITE AND VERIFY command is issued instead of a WRITE command. If the WRITE AND VERIFY command fails, the RAID controller can issue a REASSIGN BLOCKS command for the bad block and re-issue the WRITE AND VERIFY command. If WRITE AND VERIFY commands are not supported, then the system can use a READ command with the “Force Unit Access” flag bit being set to “1” to verify the written data. Further, the WRT may be combined with Bad Data Table (BDT) to reject a Read Request from the host for a matched LBA (that is listed therein) because the data in the addressed block is known incorrect when a write recovery action is not warranted.

Abstract: A method and apparatus for quiescing a system storage device wherein cache lines associated with a system storage device to be quiesced are flushed using a stripe lock mechanism to find and flush cache data associated with the given system storage device. Dirty cache lines are associated with a stripe lock, and that stripe lock will be in the active state or the clearing state. The stripe locks are also maintained on a linked list per a system storage device. In the normal life cycle of a stripe lock, if the partner controller requests a lock over part of the extent of an active lock, the active lock will go to the clearing state. Data in the extent of the now clearing lock is flushed. For performing a quiesce, stripe locks for the given system storage device are set to clearing on a plurality of controllers, thus causing the flush. The quiesce mechanism then only needs to wait until stripe locks have been cleared for the system storage device.

Abstract: A method and apparatus for automating the convergence of tap weights in an equalizer for a data channel is disclosed. The automated equalization method is contained within the channel and obtains a temporary copy of each of a plurality of current tap weights from a current tap weight memory, determines a direction for modifying the temporary copy of each of the plurality of current tap weights, constrains the modifications to the temporary copy of each of the plurality of current tap weights to produce adjusted tap weights and at the end of a read operation, stores the adjusted tap weights to the current tap weight memory for use during a next read operation.

Abstract: An improved thermal asperity detector is disclosed for detecting short thermal asperities using a variable time threshold. The thermal asperity detector includes a saturation detector, and a comparator system. The comparator system may include a polarity latch, a processor, a level comparator and a timing comparator. The saturation detector compares a programmable saturation threshold to an A/D sample to generate an enable signal in response to the A/D sample exceeding the saturation threshold. The polarity latch receives the A/D sample and the enable signal, and records the most significant bit of the A/D sample to identify the polarity of the saturation and to provide an output signal representative thereof in response to the enable signal. The processor generates a threshold level control signal based upon a programmable level threshold and the polarity latch output signal.

Abstract: A method and apparatus for optimizing the seek/settle performance of a storage device. The present invention measures the seek/settle performance for each individual head and selects the heads with the best seek/settle performance, i.e., access performance. The invention includes a processor for calculating velocity deviations for each of the plurality of heads to determine a set of suitable seek heads from the plurality of heads, a head selection circuit for switching from a current head to a preferred head from the set of suitable seek heads and an actuator controller for seeking with the preferred head to a virtual track corresponding to a target track. The processor calculates a preferred/target runout difference for smoothing the settle of the preferred head and the head selection circuit switches from the preferred head to a target head aligned with the target track.

Abstract: A test device is formed on a chip which allows the susceptibility to failure of functional circuitry formed on the chip to be tested. The test device allows aggressive design of chips which include sensitive circuitry, such as precharged dynamic logic, by testing whether deviations from the design specification introduced during manufacturing of the chip are sufficient to cause failure of the functional circuitry.

Abstract: A magnetic head position detecting method is provided in which a first and a second position detection signal representative of a particular position of a magnetic head with respect to a magnetic disk is obtained. The first and the second position detection signal preferably is obtained by utilizing a burst pattern formed on the magnetic disk. Subsequently, a third position detection signal is generated by multiplying the first and the second position detection signals by a predetermined gain so that the third position detection signal changes linearly. The particular position of the magnetic head is detected by using the third position detection signal. In addition, a magnetic disk apparatus implementing the magnetic head position detecting method is provided.

Abstract: A mechanism for compensating the servo data in a disk storage drive is provided. On each recording surface of a disk, a plurality of servo regions are diametrally formed in data regions along the diametral direction of the disk. In the servo region, a gray code (cyclic binary code) representing the address of a data track is recorded so as to correspond to the data track, and a burst pattern as a signal for positioning the head on the track are recorded. In the data track region, tracks are formed at a predetermined pitch P and in the tracks, a plurality of data is recorded. ID (Identification) is the identification information of the individual data. A servo compensation signal region is formed at a position sandwiched by the data region and the servo region known as the write recovery area. This is to compensate the servo signal in the servo region, thereby to enable error recovery when a read error or the like occurs in the servo region.

Abstract: A position control method for use with a hard disk drive or other rotating body is provided. A radial position of a rotating body corresponding to an object to be controlled is detected as a current object position. Subsequently, a control operation signal is generated which is representative of a deviation between a target object position expressed in terms of the radial position of the rotating body and the current object position detected. In addition, an actuator manipulation-amount signal is output which is derived from the control operation signal. This actuator manipulation-amount signal is formed by selectively summing an integration signal with either a first or a second control signal. The first control signal is a function of the current object position. The second control signal is a function of a predicted object position at a second predetermined time after generation of the control operation signal.

Abstract: An improvement in an interleave type error correction method in which more errors can be corrected with less correction codes is provided. Array patterns of code words constituting the information code is form by interleaving. The array patterns comprise a plurality of sequences of a plurality of code words. Correction codes are added to the sequences so that a total number of the correction codes added to a selected sequence is greater than a total number of the correction codes added to the other sequences. An error correction is executed in the selected sequence by identifying a position of an error as a consecutive error code position, when the selected sequence is determined to contain said error having a characteristic feature that the error extends over other sequences. A code word of a position corresponding to said consecutive error code position of the selected sequence among code words in the other sequences is recognized as an erasure.

Abstract: A load beam for a data storage device having a first end operatively configured for connecting to a head actuator arm and a second end operatively configured for supporting a signal transducer head is provided. The load beam has a flange with a bent portion. The bent portion is arranged by bending the standing portion of the flange in the middle thereof outwardly from the load beam. The bent portion is arranged so that it progressively becomes wider as it runs toward the end of the load beam. The flange is adapted to be nearly flush with a flat base surface at the end of the load beam so as not to have a standing portion and such that signal wires may be connected to a signal transducer head without being unduly bent.

Abstract: A charge pump that receives complimentary metal-oxide semiconductor (CMOS) input signals, has high noise immunity, low static error and works at low power supply voltages. The charge pump includes a current switch for receiving a control signal from a control circuit and for generating a charge signal, a loop filter having a first and second node, and a common-mode loop for sensing the charge signal from the current switch and for providing a voltage level adjustment signal to the first node of the loop filter in response thereto. The common-mode loop includes a sensing circuit for sensing the voltage level at the first and second node, an averaging circuit for producing an averaged voltage signal, a comparing circuit for comparing the averaged voltage signal to a reference signal to produce a feedback control output signal, and a feedback current source for adjusting the voltage level at the first node of the loop in response to the feedback control output signal.

Abstract: A disk drive having embedded servo information accesses data without using sector identifier recorded in each sector. When a signal sector pulse signal (SP) at the end of a servo area is detected in a dead state during start up, a first data state for the start of a sector transits to a second data state for the litter region of the sector being divided in accordance with the capacity stored in a current sector's pointer register. At the beginning of the sector, the contents of a next sector's pointer register is stored in current sector's pointer register and the contents of a next sector's operation register is stored in a current sector's operation register. Upon completion of sector processing, the first data state is maintained when the next sector is contiguous. When a terminate instruction is stored in current sector's operation register, the process moves to dead state. When the servo area arrives, the process moves to idle state.