Abstract: In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. The address generator formulates addresses as a function of distance from the origin of the desired destination area in a destination memory to the requested position in the destination area. A plurality of context drawing commands is used to define a desired context in which drawing graphics commands operate. Different parts of the context are changeable/redefinable independently of the other parts. Graphics commands have a format of multiple fields having corresponding parameters arranged in order of common use of the parameter such that fields of less commonly used parameters are at an omittable end of the format. Raster drawing commands are delimited by a beginning and end indicator to form a drawing unit. For clip list processing, a drawing unit is stored as a single occurrence in the system command buffer.

Abstract: A driver circuit employs an N-channel pull-down transistor of relatively small size, directly connecting an output node to ground, and another path consisting of a pair of series-connected N-channel transistors connecting the node to ground; the lower of these is driven by the logic voltage which is applied to the gate of the pull-down, and the other has its gate connected to the output node. Two parallel discharge paths are thus provided for the output node, one through the small pull-down transistor, and a second through the (larger) series transistors. When a returning wave from the output node (due to transmission line effects) hits the driver circuit, the series transistors turn off, but the pull-down transistor is still on keeping the driver output node at a valid "low." In cases of mismatch or noise, the pull-down transistor will help absorb refections or ringing.

Abstract: A modeling system provides a display of a computer system's configuration along with selected system metrics. An operator can change the configuration by using the display and display commands. Metrics representative of the performance of the computer system would then be determined for the changed configuration, and could presented along with the display of the new system configuration.

Abstract: A process for transferring data via DMA between a system resource and a controller via switching logic. During a setup write transaction, the switching logic is set up to enable DMA data to be transferred between a particular system memory and a selected system resource. The setup write transaction also is used to initialize the DMA byte counter. During a subsequent write transaction, DMA pointer registers are initialized with appropriate starting addresses. The controller then transmits a DMA start code and the system resource responds by transmitting an acknowledge code. At that time, DMA data is transmitted between the controller and the system resource via the switching logic.