Abstract: An electrically programmable, non-volatile resistive memory includes an array of memory cells, a plurality of bit lines, and a plurality of word lines. Each memory cell comprises a resistive element and a Schottky diode coupled in series and having first and second terminals. Each bit line couples to the first terminal of all memory cells in a respective column of the array. Each word line couples to the second terminal of all memory cells in a respective row of the array. The resistive element for each memory cell may be formed with a film of a perovskite material (e.g., Pr0.7Ca0.3MnO3). The Schottky diode for each memory cell may be formed by a thin film of amorphous silicon. The films for the resistive element and Schottky diode for each memory cell may be stacked in a compact island at the cross point between a bit line and a word line.

Abstract: Techniques to suppress noise from a signal comprised of speech plus noise. In accordance with aspects of the invention, two or more signal detectors (e.g., microphones) are used to detect respective signals having speech and noise components, with the magnitude of each component being dependent on various factors such as the distance between the speech source and the microphone. Signal processing is then used to process the detected signals to generate the desired output signal having predominantly speech with a large portion of the noise removed. The techniques described herein may be advantageously used for both near-field and far-field applications, and may be implemented in various mobile communication devices such as cellular phones.

Abstract: An acoustic echo canceller comprising an adaptive filter, a post filter, and an adjustable filter. The adaptive filter receives a reference signal and a near-end signal, cancels a portion of the echo in the near-end signal using the reference signal, and provides an intermediate signal having remaining echo not canceled by the adaptive filter. The post filter calculates the cross-correlation between the near-end signal and intermediate signal, and provides a set of coefficients based on a variable suppression parameter. The adjustable filter processes the intermediate signal based on the coefficients and provides an output signal having at least a portion of the remaining echo removed. The acoustic echo canceller may further comprise a channel control unit that provides control signals, an adjustable amplifier, a noise estimator that estimates the noise in the intermediate signal, and a noise reinsertion unit that reinserts a version of the estimated noise back into the output signal.

Abstract: Techniques are provided to suppress noise and interference using an array microphone and a combination of time-domain and frequency-domain signal processing. In one design, a noise suppression system includes an array microphone, at least one voice activity detector (VAD), a reference generator, a beam-former, and a multi-channel noise suppressor. The array microphone includes multiple microphones—at least one omni-directional microphone and at least one uni-directional microphone. Each microphone provides a respective received signal. The VAD provides at least one voice detection signal used to control the operation of the reference generator, beam-former, and noise suppressor. The reference generator provides a reference signal based on a first set of received signals and having desired voice signal suppressed. The beam-former provides a beam-formed signal based on a second set of received signals and having noise and interference suppressed.

Abstract: An embedded system comprising an embedded core, a non-volatile memory (e.g., a Flash memory or a ROM), and a volatile memory (e.g., RAM). The embedded core performs processing tasks for the embedded system. The non-volatile memory stores executable codes for the embedded core. The volatile memory stores program data and auxiliary data for the embedded core during first and second operating modes, respectively. The embedded core executes the executable codes from the non-volatile memory and operates on the program data in the volatile memory in the first operating mode, and retrieves the auxiliary data from the volatile memory and performs processing based on the retrieved auxiliary data in the second operating mode. The embedded system is fully functional in the second operating mode, and the auxiliary data may comprise (1) programming codes used to program the non-volatile memory, or (2) a test program to test the embedded system.

Abstract: Data input and output circuits that support multi data rate and a number of timing schemes. In one design, a data output circuit includes an input multiplexer, data latches, an output multiplexer, and at least one output driver. The input multiplexer receives a set of data bits in a first order (e.g., odd and even) and provides the data bits in a second order (e.g., first and second). The data latches can latch the data bits with (1) a latch signal to satisfy memory access timing requirements and (2) a data write clock signal to satisfy output timing requirements. The output multiplexer multiplexes the latched data bits to provide time multiplexed data bits. The output driver(s) provide signal drive for the time multiplexed data bits. Clock signals with various timing characteristics can be used to allow the data output circuit to satisfy various timing requirements.

Abstract: A clock generation system includes an oscillator and one or more clock generators. The oscillator provides inphase and quadrature oscillator signals having a fixed frequency. Each clock generator receives the oscillator signals and generates a respective output clock signal. Within each clock generator, two weight generators receive two sequences of phase values and generate weights for two analog signals. Two signal generators multiply the inphase and quadrature oscillator signals with the weights from the two weight generators and provide the two analog signals having leading edges determined by the two sequences of phase values. A digital clock generator generates a DCLK signal based on the two analog signals. A divider divides the DCLK signal by N in frequency and provides the output clock signal. A phase generator generates the two sequences of phase values for the two analog signals based on a frequency control value and a phase offset value.

Abstract: Techniques for canceling echo and suppressing noise using an array microphone and signal processing. In one system, at least two microphones form an array microphone and provide at least two microphone input signals. Each input signal may be processed by an echo canceller unit to provide a corresponding intermediate signal having some echo removed. An echo cancellation control unit receives the intermediate signals and derives a first gain used for echo cancellation. A noise suppression control unit provides at least one control signal used for noise suppression based on background noise detected in the intermediate signals. An echo cancellation and noise suppression unit derives a second gain based on the control signal(s), cancels echo in a designated intermediate signal based on the first gain, and suppresses noise in this intermediate signal based on the second gain. The signal processing may be performed in the frequency domain.

Abstract: Floating-point units (FPUs) and processors having a “flush-to-nearest” operating mode that provides improved accuracy over a conventional “flush-to-zero” mode. The FPU or processor includes an operand processing section and an operand flush section. For each floating-point operation, the operand processing section receives and processes one or more input operands to provide a preliminary result. The operand flush section determines whether the preliminary result falls within one of a number of ranges of values and sets the preliminary result to one of a number of set values if the preliminary result falls within one of the ranges. In a specific implementation, a first range of values is defined to include values greater than zero and less than half of a minimum normalized number (i.e., 0<|y|<+amin/2), a second range of values is defined to include values equal to or greater than +amin/2 and less than +an, (i.e.

Abstract: A text-to-speech conversion system that includes a first module to convert text into words, a second module to convert words into phonemes, a third module to map phonemes to sound units, and a storage unit to store speech representations for a library of sound units. The first, second, and third modules and the storage unit are implemented within a single integrated circuit to reduce size and cost. The system typically further includes a ROM to store the codes for the modules, a RAM to store the text and intermediate results, a processor to execute the codes for the modules, a control module to direct the operation of the first, second, and third modules. The storage unit may be implemented with a multi-level, non-volatile analog storage array and may be programmed with a new library of speech representations by a programming module.

Abstract: A video decoder for decoding a composite video signal. The decoder includes an analog-to-digital converter (ADC), an input resampler, and a Y/C separator, all coupled in series. The ADC receives and digitizes the composite video signal to generate ADC samples. The input resampler receives and resamples the ADC samples with a first resampling signal to generate resampled video samples. The Y/C separator receives and separates the resampled video samples into luminance and chrominance components. The Y/C separator includes a delay element configured to receive the resampled video samples and provide a variable amount of delay. The variable amount of delay can be adjustable from line to line, and is typically based on an approximated duration of a video line.

Abstract: A dummy content-addressable memory (CAM) cell and a dummy ternary CAM cell are connected to each row in a CAM and a ternary CAM array, respectively, to enable a differential match line sensing based on the content stored. The ternary CAM cell is for a differential match line sensing in low power applications. A method includes generating a voltage difference between a match line signal and a reference line signal, and then detecting and amplifying the voltage difference to determine a match or a mismatch.

Abstract: Techniques to improve the operating speed and switching performance of a latch having an integrated gate. In one design, the latch includes first and second differential amplifiers and a feedback circuit (e.g., a third differential amplifier). The first differential amplifier has a number of non-inverting inputs (e.g., configured to implement an OR function) and an inverting input, receives and senses input signals applied to the non-inverting inputs during a “sensing” phase, and provides a differential output. The second differential amplifier latches the output during a “latching” phase. The feedback circuit detects the non-inverting output and provides a control signal for the inverting input of the first differential amplifier. The feedback circuit can provide positive feedback, and can dynamically adjust the inverting input to provide improved switching performance.

Abstract: Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. The intermediate result from the multiplier unit is processed (i.e., rounded) into representations that are more easily managed in the adder unit. However, some of the processing (i.e., normalization and exponent adjustment) to generate an IEEE-compliant representation is deferred to the adder unit. By combining and deferring some of the processing steps for the intermediate result, circuit complexity is reduced and operational performance is improved.

Abstract: A feature in a web browser allows a user to specify all or a portion of a web page and to schedule and/or how often to send the current contents of that portion of the web page to a receiving device such as a alpha-numeric pager or cellular telephone, thereby reducing or eliminating the need for having a browser on the device.

Abstract: Techniques to more accurately read values stored in data cells. In an aspect, one reference cell is provided for each group of data cells having similar configuration (e.g., similar layout and orientation). For split-gate memory cells arranged in pairs, each pair includes two data cells implemented as mirrored image of one another. Two reference cells may then be used, one reference cell for each data cell in a pair. In another aspect, the data paths for the reference and data cells for read operation are matched. This matching may be achieved by using the same circuit design for the data and reference sense amplifiers, using the same layout and orientation for the sense amplifiers, matching the lines for the two data paths, matching the structure (e.g., length and width) and the diffusion region (e.g., doping concentration and contact) for the sense amplifiers and lines, and so on.

Abstract: A semiconductor device is provided comprising a die. A first set of plural components, other than interface components, are located on the die surface. A first conductor located on the die surface connects to each component of the first set. A second set of plural components, other than said interface components, are located on the die surface. A second conductor located on the die surface connects to each component of the second set. A bonding pad is located on the die surface such that the first set of components lie between the bonding pad and an edge of the die and the second set of components lie between the bonding pad and an opposing edge of the die. The bonding pad is for receiving or transmitting one or more signals via the first and second conductors. At least one lead frame finger extends to an edge of the die but does not overlie the die. A bonding wire connects the at least one finger to the bonding pad.