Abstract: A memory controller generates control and address signal for accessing a non-volatile memory having a plurality of addressable cells. Each cell of the non-volatile memory includes a floating gate transistor (e.g., Q15) capable of storing charge (representing a binary 1 or 0) for extended, although not indefinite, periods of time. To refresh any charge that leaks off the floating gate, refresh circuitry (e.g., Q17-Q19) is provided to restore the charge on the gate to its original logical state. This refresh circuitry may be activated at "power-up." Each of the transistors in the memory are preferably thin film, amorphous silicon, "N" type transistors, including the floating gate transistor.

Abstract: A data processing includes an on-line, interactive, intelligent help system which provides suggestions as to actions a user can take after entry into the system of an erroneous command or a question. The system also responds with explanations of why the suggestions were made and how they work. The system includes a natural language analyzer for converting the questions into goals. A knowledge base and an inference engine further analyze the goals and provide one or more suggestions on how to achieve such goals. An explanation generator uses such analysis to dynamically generate the explanations which are tailored to the user's goal.