Abstract: A work station, including a central processing unit (CPU), first, second and third integrated circuit interface chips connected to an external bus, memory and peripheral unit, respectively, and a local bus connected to the CPU and interface chips. Each chip includes an internal bus interconnecting operating units disposed therein. Each interface chip is adapted to operate at the same clock frequency as the CPU, but with operational signals generated on its respective internal bus independently of the CPU.

Abstract: An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.

Abstract: A differential inverter such as may be used in an oscillator circuit. The differential inverter is connected between first and second current sources. The differential inverter includes first and second single signal CMOS inverters connected in parallel between the first and second controlled current sources. Each of the current sources is a MOS transistor. A bias circuit is connected to the control gates of the MOS transistors and provides bias signals thereto, the bias circuit includes a variable current source with bias signals being generated in response to the current flow in the variable current source.

Abstract: A method for designing a scan path to connect flip-flops in a logic circuit. Test patterns are created by the circuit designer. The circuit and test patterns are then simulated to determine potential faults in the circuit which are not detected by the patterns and not observable at any flip-flop in the circuit. The number of such faults is then reduced. For example, the test patterns can be modified and/or redundant circuit elements can be removed. A subset of flip-flops where undetectable faults are observable are then identified and connected in a scan path. Scan times can also be selected. The method may be extended to include the actual testing of the logic circuit.

Abstract: A process for producing self-aligned titanium silicide. A silicon substrate is provided, silicon electrode and oxide insulator regions are formed on the substrate, and a titanium layer overlying the electrode and insulator regions is formed. The device is heated in an oxygen rich environment to form titanium silicide overlying the electrode regions and to form titanium oxide overlying the insulator regions and metal silicide.

Abstract: A method for cleaning data elements in a memory system accessible by a bus master. A first data element is transferred between the bus master and a fast memory while writing the first element to a dirty element register within the memory system. The first element is then cleaned by writing it from the register to a slow memory within the system without delaying memory access requests for the fast memory.

Abstract: A method for retransmitting selected data elements read from a memory. A first sequence of individually addressable data elements d.sub.1, d.sub.2, . . . , d.sub.n are read from the memory. First and second signals indicate whether each data element was read without or with, respectively, a transmission error. A second sequence of data elements d.sub.i, d.sub.i+1, . . . , d.sub.n, where d.sub.i is the first data element of the first sequence to have a transmission error is then retransmitted.

Abstract: A method for high speed data transfer between a user operated PC and a remote PC. First, a link is established between the user operated PC and remote PC. A data file is transferred from the user operated PC to an interfacing device connected to the user operated PC. The file is then formatted in the interfacing device, and transmitted therefrom to the remote PC over an ISDN line. A second data file may be transferred from the remote PC to the user operated PC contemporaneously with the transferring, formatting and transmitting of the other data file.

Abstract: An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.

Abstract: A device and method for approximating the square root of a binary number N. The device includes hardware for storing N, and a result register for storing x.sub.n, where x.sub.n is a successive approximation of r. The device also includes hardware for iteratively replacing x.sub.n with x.sub.n+1, starting with n=0, where x.sub.n+1 =(Ax.sub.n +N-x.sub.n.sup.2)/A, and x.sub.0 is within a predetermined range. "A" is a multiple of 2 so that an operation involving a product or quotient with "A" is effected by a shift operation.

Abstract: The subject invention is a FIFO memory system and method for buffering data between two data busses. The system comprises a RAM memory, write and read pointer registers, an offset generator, a programmable offset register, and a comparator. The write pointer register stores the address of the next data element to be written into the RAM memory, and the read pointer register stores the address of the next data element to be read from the RAM memory. The offset generator compares the contents of the registers, and generates at an output thereof an offset signal representing the amount of memory space occupied. The programmable offset register provides a programmed offset signal. The comparator compares the offset signal and the programmed offset signal, and provides a ready signal when the offset signal is greater than or equal to the programmed offset signal.

Abstract: A method and system of maintaining coherency for a data block transferred from a main memory to a cache memory. The data transfer is recorded in a tag register in the main memory. An overwrite of the data block is detected by comparing main memory data writes with the recorded transfer. The cache memory is only notified in the event an overwrite is detected. An invalid flag is then set in the cache.

Abstract: A process for forming field oxide regions between active regions in a semiconductor substrate. Pad oxide, polysilicon and first silicon nitride layers are successively formed over substrate active regions. The first nitride layer, polysilicon layer, pad oxide layer and a portion of the substrate are then selectively etched to define field oxide regions with substantially vertical sidewalls. A second silicon nitride is provided on the substantially vertical sidewalls, and field oxide is grown in the field oxide regions. The first silicon nitride, polysilicon and pad oxide layers are then removed. The presence of the polysilicon layer prevents the formation of a sharp corner between the field oxide and active regions if an overetch occurs during the removal of the pad oxide layer.

Abstract: A system and method for requesting access to refresh a computer memory. Two lines are connected between a timer and arbiter. A memory refresh request signal is provided on the first line and is accorded a relatively low priority by the arbiter. If the first request is not granted within a predetermined period of time, a second memory refresh request signal is provided on the second line and is accorded a relatively high priority by the arbiter.

Abstract: The subject invention is a an improved memory system and method for a data processing system. The method involves the overwriting of a first data word in a memory by a second data word, wherein each addressable location in the memory holds a data element with N data words. The method comprises reading the data element which includes the first data word from the memory into a first cache register, simultaneously writing the second data word to a second cache register, and then writing into the main memory the second data word along with all of the words of the data element in the first cache register save the first word.

Abstract: A method of transferring data from a computer to a remote entity. A predetermined block count is stored in the computer. One or more data blocks are moved from the computer to one or more buffers, respectively, in an interfacing device. The block count is decremented for each of the data blocks so moved. One or more of the data blocks are then transmitted from the interfacing device to the remote entity. An acknowledge signal is received from the remote entity for each data block received by the remote entity, and the block count is incremented for each acknowledge signal so received.

Abstract: A method for determining a copy-on-write condition in a UNIX process which includes providing a page table with an entry identifying a memory page location, and providing the entry with a copy-on-write bit. The bit is transferred to a circuit for processing and, if the memory page is to be written to and the copy-on-write bit is set, a copy-on-write fault is generated.

Abstract: A nonvolatile memory device comprising first and second transistors connected between respective first and second terminals and a reference potential terminal, the transistors having first and second floating gates, respectively, for storing complementary charges. The device further comprises first and second input lines capacitively coupled to the gates, and means for providing a biasing voltage slightly in excess of the threshold voltage of the transistors to the input lines.

Abstract: An encoder and a decoder is provided with each being usable independently of each other for improving the dynamic range of clipped speech digital systems by providing amplitude components to the clipped digital signal. The encoder processes an audio input signal along two signal paths, the first signal path including a clipper and digitizer means for forming a digitized clipped signal. The second signal path includes a rectifier, envelope detector and digitizing means for forming a digitized signal having amplitude components. Both digitized signals may then be transmitted to the decoder for reconstruction or stored for reconstruction at a later time.

Abstract: A system comprising a memory for transferring m data bytes at a time, first and second busses each having a width of less than m data bytes, first parallel m byte wide read and write registers connected between the first bus and the memory and second parallel m byte wide read and write registers connected between the second bus and the memory.