Abstract: A procedure is used to provide data structures that handle large numbers of active data entries and a high rate of additions and deletions of active entries. The procedure utilizes one or more of the following modifications. Timers are removed from individual session table entries and are linked via pointers. Bilateral links are established between the session table and the timer structure. Aging/timer checks are applied to the timer control block (TCB). A chain of TCBs, optionally including an excess of blocks, may be used along with packing of multiple TCBs into a single memory location. This excess of blocks permits a terminated session to continue to occupy a TCB until the timer process progresses to that block location in the chain of blocks.

Abstract: The present invention provides a method and system for providing a legal sequential combination of commands for verification testing of a computer system. Executable test commands are used to form sequentially ordered “buckets” of commands, wherein each bucket command sequence is legal under at least one rule. The buckets may be arranged in any sequential order, wherein a composite command sequence of the combined commands remains legal under the at least one rule. A further advantage of the invention is that wait/noop commands may be inserted within and between the buckets, extending the testing capabilities of the present invention into corner cases.

Abstract: A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collisions of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 216 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, Li field and UUI field with the two tables.

Abstract: A programmable state machine is incorporated into the core of a network processor (NP) to monitor the utilization of different processing elements in the NP and to control the power state of each element as a function of past and predicted utilization. The state machine can be used to control a centralized power management control unit or to control a distributed power management unit where each processing element includes its own state machine. The function of the power management state machine can be implemented in any combination of software and/or hardwired logic, depending on the system design requirements. The monitoring and control are implemented through the use of a power management state change algorithm. The determination of the power state of a processing element accommodates interdependencies between the elements. It also makes adjustments in gain factors in response to actual performance and utilization of the network processor.

Abstract: A method for sequencing delivery of information packets from a router having several processing elements to a receiving processing installation, wherein delivery of the packets must be completed in the order the packets arrive at the router. A linked list of packets is formed in the order they are received at the router, and each packet fragmented into successive fragments. Each fragment is processed at the router. The last fragment of each packet in each linked list is labeled with the sequence in which the packet was received, and enqueued in the order labeled for each last fragment on each linked list. Each fragment of each packet is delivered as processed, except the last fragment of each packet on its linked list to the receiving processor installation, and thereafter, transmitting the final fragment of each packet after processing only if that fragment is at the head of the queue.

Abstract: Data communication in network traffic is modeled in real time and is analyzed using a 2-state Markov modified Poissen process (MMPP). The traffic inter-arrival times for bursty and idle states define a transition window [?1max, ?2min] represented by the boundary values ?1max for the inter-arrival time for bursty traffic, and ?2min for the inter-arrival time for idle traffic. Changes in the values of ?1max and ?2min are tracked over time, and the size of the transition window is enlarged or decreased based upon relative changes in these values. If the inter-rival times for the bursty state and the idle state become approximately equal, the model defaults to a single state model. The modeling is applicable to the synchronization of polling and blocking in a low-latency network system. This permits the adoptive selection of poll or block to maximize CPU utilization and interrupt latency.

Abstract: A mobility assistance vest can be easily donned by placing the vest inside up under the dog, then pulling the right and left side sections together over the top line fastening the Velcro strips, and then pulling the chest section by the front shoulder straps through the front legs and securing the shoulder straps to the side sections on either side of the neck. The semi-detachable handle straps at the front legs are then crossed to the opposing side and attached with a snap to D-rings on the shoulder handles for the human handler to provide counter weight or upward support as they both descend the stairs side by side. Alternatively, the detachable handle straps at the front legs can be attached with the snap connector to the D-rings on the rear section of the vest to provide support for assisting the canine while ascending stairs, walking and standing up.

Abstract: A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS.

Abstract: Packets or frames of data may be compressed, encrypted/decrypted, filtered, classified, searched or subjected to other deep-packet processing operations before being distributed through the internet. The microprocessor system and method of the present invention provide for the orderly processing of such data packets without disrupting or changing the sequence in which the data is intended to be transmitted to its destination. This is achieved by receiving frames into an input buffer for processing. Associated with this input buffer is a unit for determining the operation to be performed on each frame. An arbitrator assigns each frame to a processing core engine. An output buffer collects the processed frames, and a sequencer forwards the processed frames from the output buffer to their destination in the same order as received by the input/output buffer. Maintaining the sequence of data transmission is particularly useful in voice transmission, such as videos and movies.

Abstract: Self-similar data communication in network traffic is modeled real time and is analyzed using a Markov modified Poissen process (MMPP) to characterize the traffic flow and to accommodate high variability in traffic flow from one time period to the other. The analysis is performed at multiple time levels using a bottom-up approach. The parameters of the model are adjustable at each level according to the traffic parameters at that level. Each model consists of 2 states of network traffic behavior comprising a bursty state representing heavy traffic conditions and an idle state representing light traffic conditions. A transition window defines the upper time interval for the receipt of packets in the bursty state and the lower time interval for the receipt of packets in the idle state. If the inter-rival times for the bursty state and the idle state become approximately equal, the model defaults to a single state model.

Abstract: A wireless system that detects the presence of a child in a safety seat located in the passenger cabin of a vehicle includes a controller responsive to signals generated by sensors monitoring predefined functions of the vehicle, RFID tag device attached to the safety seat and RFID tag reader mounted in the cabin. The system generates control signals which activate an alarm, open the doors of the vehicle and roll down windows if the child is left in the safety seat of an unattended vehicle.

Abstract: A method and apparatus are provided for determining power events on an I/C chip for undissipated power to the chip, and wherein the chip includes a plurality of separately regulatable power consumers. A structure is provided for monitoring the occurrence of each power event to each power consumer, and determining the dissipation of power from each power event, and controlling power used by the chip responsive to the amount of undissipated power.

Abstract: A packaging apparatus comprising a pulp-based composition that provides protection to an equipment component (or other fragile or breakable item), provides ease in use during pre-packing and packing of an equipment component for transport, does not require the need for additional packing components in combination with the packaging assembly, provides shock protection during transport, is reusable, and is economically suited for its end use, is provided for. In accordance with one aspect of the present invention, the present invention is a molded, one piece packing assembly comprised of substantially a pulp-based composition. The present invention is advantageously designed using specific geometries which, contrary to traditional designs, benefit from the stressing and flexing characteristics of paper fiber.

Abstract: Provided is an information processing apparatus that performs a desired process by a user while preserving a low consumption power state. The information processing apparatus comprises an electric power button for starting operation of an operating system when receiving an input from the user, a controller part for receiving an input to a switch other than the electric power button in an operation termination state in which the operation of the operating system is terminated, an execution part for executing a predetermined processing while preserving the operation termination state when the input to the switch is accepted by the controller part in the operation termination state.

Abstract: A method of forming a member for joining to form a composite wiring board. The member includes a dielectric substrate. Adhesive tape is applied to at least one face of said substrate. At least one opening is formed through the substrate extending from one face to the other and through each adhesive tape. An electrically conductive material is dispensed in each of the openings and partially cured. The adhesive tape is removed to allow a nub of the conductive material to extend above the substrate face to form a wiring structure with other elements.

Abstract: A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and isolatable from, a given power source. At least one MEMS is positioned to selectively connect and disconnect said at least one connection to and from said given power source.

Abstract: The invention provides replacement operation code for specific defective lines of operation code contained in a ROM often on an ASIC chip which code is used in a processor. ROM memory constitutes the best use of chip space and is the most economical to manufacture of all of the various options. ROM memory is not changeable after it is set in ROM and, hence, if there is any change in the code (hereinafter sometimes faulty code) required after the code has been incorporated in the ROM memory, such change cannot be made in the ROM itself without replacing the entire ROM. The present invention allows change in any specific lines of faulty contained in ROM without replacing the entire ROM, and provides for changing only the faulty lines of code. It also allows the new code to have the same, more, or fewer lines than the faulty code.

Abstract: A method and system for efficient scaling in the transform domain, wherein transform coefficient data is provided as an input to a data processing system and scaled in the transform domain by application of a combined matrix. Some embodiments utilize discrete cosine transform data. One embodiment of the invention generates a combined matrix for one-dimensional scaling by selecting a rational scaling factor and matrix dimension value, generating a matrix with some zero values, applying a one-dimensional inverse transform, regrouping, and applying a one-dimensional forward transform. One application of the invention performs up-scaling operations, and another performs down-scaling operations. The invention also provides for two-dimensional scaling by selecting horizontal and vertical scaling parameters and generating first and second combined matrices responsive to the parameters and combining them into a single combined matrix. The invention may also incorporate a predetermined cost function.