Abstract: A DC converter for stepping down DC voltage having two input terminals (E1, E2) to be connected to an input DC voltage source with a high voltage level; two output terminals (A1, A2) for taking a regulated low output DC voltage; a coil (TS) having a center tap (MA) and connected at one end (TA1) with a first one (E1) of the input terminals via an electronic switch device (MOS) and at the other end (TA2) with the second input terminal (E2) via a first capacitor (C1); the charging voltage of the first capacitor (C1) forming the output DC voltage; a second capacitor (C6) connected at one end with a node located between switching device (MOS) and coil (TS) and at the other end with the center tap (MA) via a first diode (D2); a control device (EV, PWM for comparing the charging voltage of the second capacitor (C6) with a reference voltage (REF) and rendering the switch device (MOS) conductive and non-conductive with a pulse-frequency modulated and/or pulse-width modulated switching pulse sequence depending on the

Abstract: A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.

Abstract: An electronic semiconductor device (20) with a control electrode (19) consisting of self-aligned polycrystalline silicon (4) and silicide (12), of the type in which said control electrode (19) is formed above a portion (1) of semiconductor material which accommodates active areas (9) of the device (20) laterally with respect to the electrode, has the active areas (9) at least partially protected by an oxide layer (10) while the silicide layer (12) is obtained by means of direct reaction between a cobalt film deposited on the polycrystalline silicon (4) and on the oxide layer (10). (FIG.

Abstract: A voltage generator for electrically programmable non-volatile memory cells, constructed of a number of charge pump circuits having inputs controlled by a number of phase generators. The charge pump circuits are laid as pairs of first and second charge pump circuits. The first charge pump circuits are active when the second charge pump circuits are inactive, and vice versa.

Abstract: A multiplier circuit multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary factors, and a combinatorial network provides the final sum of the partial products. The partial multiplications that include at least one of the more significant bits of the operands are performed by logic gating circuits which can be enabled to also carry out a two's complement partial multiplication. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values unrelated to the factors.

Abstract: A nonvolatile ferroelectric memory that reduces the number of cycles of reference cells to extend lifetime of memory. A reference cell of the memory is activated to provide a reference voltage to a sense amplifier only when the sense amplifier needs the reference voltage. The memory comprises a plurality of cells arranged in a matrix form and including memory cells and reference cells, and a plurality of sense amplifiers arranged in a row of the matrix, in which each sense amplifier compares voltages induced from a reference cell and a selected memory cell to read information stored in the selected memory cell, and in which each reference cell is activated only when both a selection signal from a column address and a word line connected to said reference cell are enabled.

Abstract: A boosting circuit supplied by a first voltage level and a second voltage level, and having an output line capable of taking a third voltage level, the circuit having at least two distinct circuits for generating the third voltage level, the at least two circuits selectively activatable for generating the third voltage level and selectively coupleable to the output line.

Abstract: An electromagnetic head for a storage device comprises a magnetic core forming a magnetic circuit, and a magnetoresistive means. The magnetic core is interrupted by an air-gap, thereby separating a first pole and second pole of the magnetic core. The magnetoresistive means is disposed in the region of the air-gap, and is connected to the magnetic core so as to be connected in the magnetic circuit.

Abstract: A switched capacitor wherein one of the plates of the capacitor to be switched is fed with the input signal via a transistor switch receiving as control signal at the gate thereof a pulse train with predetermined frequency. For compensating the parasitic capacitance of the transistor switch, a compensation component is located between the transistor switch and the capacitor to be switched. This compensation component is formed as an incomplete transistor structure, such as only 1/2 of a transistor, has a drain region in common with transistor switch and has an insulated gate. The parasitic capacitance of the compensation component thus is established mainly by the capacitance between the insulated gate and the drain region and thus corresponds to the parasitic capacitance of the transistor switch, whereby complete compensation with optimized charge transfer is achieved.

Abstract: A voltage regulator providing smooth variation of an absorbed current having a first capacitor parallel-connected to a load, which is in turn connected to a supply voltage; a transconductor coupled between the supply voltage and the load and whose output voltage supplies the load; a differential amplifier coupled between the output of the transconductor and the supply voltage, and further coupled to the input of the transconductor, a second capacitor coupled between the supply voltage and the input of the transconductor; and a pair of diodes coupled between the output of the transconductor and the first capacitor and configured to introduce a zero in the transfer function of the voltage regulator that is suitable to compensate for a pole generated by the first capacitor.

Abstract: The read circuit has an array branch connected to an array cell, and a reference branch connected to a reference cell; the array branch presents an array load transistor interposed between a supply line and the array cell, and the reference branch presents a reference load transistor interposed between the supply line and the reference cell; and the array and reference load transistors form a current mirror wherein the array load transistor is diode-connected and presents a first predetermined channel width/length ratio, and the reference load transistor presents a second predetermined channel width/length ratio N times greater than the first ratio, so that the current flowing in the array cell is supplied, amplified, to the reference branch.

Abstract: A method for saving and restoring data in the event of unwanted interruption of programming, the control logic unit of the memory controls writing of the data that would otherwise be lost and its address, in an appropriate backup memory location. To this end, the backup memory location is maintained erased, such as to allow immediate writing of the data and its address, in case of interruption of programming. To guarantee functioning even in the absence of an external supply, appropriate charge accumulators are provided, which can guarantee availability of a write-only cycle. As soon as a voltage drop is detected, the operations in progress are interrupted, and the backup operations for the data being programmed are activated; when the memory is switched on again, it is verified whether an interruption of the writing cycle has previously occurred, and thus the data saved can be recovered into the main memory.

Abstract: The method described provides for the formation of thin thermal oxide on areas of a silicon die intended for memory cells and other components of the peripheral circuits of the memory. To improve the quality of the oxide of the cells essentially in terms of resistance to degradation due to the passage of charges through it during the operation of the memory, the method provides for a step for the high-temperature nitriding of the oxide. According to a variant, the nitrided oxide formed on the areas intended for the components of the peripheral circuits is removed and then formed again by a similar thermal oxidation treatment followed by high-temperature nitriding.

Abstract: A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.

Abstract: An audio signal processor is disclosed which has at least one audio signal input and at least one audio signal output as well as at least one control input, and an audio signal processing unit connected between audio signal input and audio signal output, the audio signal processing unit having a programmable indicator tone generator circuit to be driven via the control input and whose indicator tone signal is switched to the audio signal output in accordance with the state of the control input.

Abstract: A switching circuit comprising a supply voltage, a reference voltage, a line suitable to carry a negative voltage, an input for a control signal, suitable to supply to a first output node and to a second output node two voltages respectively equal to supply voltage and to line voltage or, alternatively, to line voltage and to supply voltage, in response to the control signal.