Abstract: A microprocessor system includes a microprocessor, a memory, and one or more direct memory access controllers, all connected to a common system bus which includes a system address bus and a system data bus. At least one of the direct memory access controllers is shared by a plurality of subsystem device controllers which may control peripheral devices having diverse characteristics. The microprocessor is limited in its instruction repertoire and may control peripheral devices only by means of an input and an output instruction. The shared direct memory access controller includes no circuitry which is specifically for controlling only a single type of peripheral device, the device dependent logic being located in subsystem device controllers. Data transfers may take place directly between the memory and, through the shared direct memory access controller, any selected one of the peripheral devices.

Abstract: A phase locked oscillator comprising a phase comparator, filter and voltage controlled oscillator coupled in conventional manner to form the forward path of the phase locked loop and a counter and logic circuit coupled to form the feedback path. An input pulse stream is applied to a monostable flip flop which responds to each input pulse to produce a pulse of predetermined length that is applied to one input of the phase comparator. The counter is coupled to receive the oscillator output pulses for counting repetitively to a predetermined count. The logic circuit responds to first and second counts in the predetermined count for respectively generating and terminating a reference pulse in response to each input pulse. The reference pulse is applied to the other input of the phase comparator which in turn provides an output signal indicative of the time displacement between each input pulse and its associated reference pulse to control the oscillator to run at a harmonic frequency of the input pulse stream.