Abstract: A null initiated priority channel monitoring system provides enhanced nonpriority signal intelligibility and/or enhanced priority channel sensitivity during sample times. The priority channel or channels are monitored during nulls in the received nonpriority signal. The system can have a minimum time period between priority channel monitoring periods to avoid substantially continuous priority channel monitoring. The system can also have a maximum time period between priority channel monitoring or sampling periods to avoid missing any priority channel signal.

Abstract: A digital communication system including an encoder and decoder for the transmission of digital information over a transmission medium, the system having automatic frame synchronization and error correction requiring a minimum of tansmission bits and decoding time. The encoder processes a data stream and generates a transmission bit stream of N bits using convolutional encoding, autosynchronization sequence combining, and bit interleaving. The multi-phase sequential decoder decodes the received coded data, corrects transmission errors and automatically achieves frame synchronization from P selected phases of the received data. This is accomplished by selecting the phase of the received data with the best metric, bit de-interleaving, removing the autosynchronization sequence and comparing the received data of the selected phase with the extended code word subsets from the node having the best metric.

Abstract: Improved noise reducing circuitry for high frequency signal sideband (SSB) receivers is described that substantially eliminates interference caused by impulse noise from a noise source 160. The SSB receiver includes first and second mixers 102 and 106 intercoupled by a crystal filter 104 having a passband that is approximately the same as the noise bandwidth of the antenna circuitry 100 when the SSB receiver is tuned to the lower frequency in its frequency band. A second intermediate frequency (IF) signal from second mixer 106 is coupled to an IF amplifier 122 and a noise amplifier 126. An envelope decector 128 is coupled to the output of noise amplifier 126 and provides an output signal having a magnitude proportional to the envelope of the noise amplifier output. Automatic gain control circuitry 132 is coupled to the output of the envelope detector for generating a gain control signal that reduces the gain of noise amplifier 126 as the magnitude of the envelope detector output increases.

Abstract: A transmitter power control circuit which provides normal power control functions, and provides a high speed loop response when abrupt changes in output power are required. The circuit utilizes an electronic switch to provide adaptive filtering to permit narrow bandwidth filtering during normal steady state operation of the transmitter and wide bandwidth filtering during desired abrupt changes in transmitter power output. This allows rapid changes in transmitter output power when desired, while substantially eliminating undesired noise during normal operation.

Abstract: An improved digital demodulator and detector for phase-shift-keyed digital signals providing coherent detection with high sensitivity and stability on noisy channels. Digital sampling is used in conjunction with a digital phase locked loop system in which basic time increments are subtracted or added to an equilibrium timing loop to provide simultaneous carrier demodulation and bit recovery.

Abstract: Multi-state control circuitry is described that can selectively couple an input signal to the positive and negative inputs of an operational amplifier depending on the voltage of a control signal. The input signal is coupled to the operational amplifier by a switch, which is enabled or disabled by the output of a voltage detector. The voltage detector enables the switch when the voltage of the control signal is less than a threshold voltage, and disables the switch when the voltage of the control signal is greater than the threshold voltage. The amplification of the operational amplifier is switched between +1 and -1 by selectively coupling a DC voltage to the positive input of the operation amplifier, depending on the current of the control signal. The DC voltage is coupled to the positive input of the operational amplifier by a second switch, which is enabled or disabled by a current detector.

Abstract: A universal crystal holder is provided which is capable of supporting piezoelectric crystals having virtually any size and shape. The crystal holder includes two support structures, each having a downwardly sloping surface for accepting a side of the crystal to be supported. Since crystals placed in the universal crystal holder of the invention are self-aligned, the placement of a crystal in the holder is easily automated.