Abstract: An apparatus and method for testing “chip scale” integrated circuits (IC's) using a vertical probe card mounted on a printed circuit board (PCB). A nesting assembly mounted over the vertical probe card includes alignment walls and an alignment plate including chamfered through holes. The alignment walls are slanted to provide rough alignment of the IC within the nesting assembly, and fine alignment of the IC is achieved when the solder balls extending from the IC are received in the chamfers formed in the upper surface of the alignment plate. Tips of formed wire probes extend from the vertical probe card towards the bottom surface of the alignment plate. When the alignment plate is pushed towards the vertical probe card by a device handler, the tips of the wire probes extend through the through-holes and pierce the solder balls of the IC, providing electrical contact between the IC and the PCB.