Abstract: Complex digital data values derived from a DSSS signal, in particular, a GNSS signal, are delivered to a general purpose microprocessor at a rate of 8 MHz and chip sums over eight consecutive data values spaced by a sampling length (TS), each beginning with one of the data values as an initial value, formed and stored. For code removal, each of a series of chip sums covering a correlation interval of 1 ms and each essentially coinciding with a chip interval of fixed chip length (TC), where a value of a basic function (bm) reflecting a PRN basic sequence of a satellite assumes a correlation value (Bm), is multiplied by the latter and the products added up over a partial correlation interval to form a partial correlation sum. The partial correlation interval is chosen in such a way that it essentially coincides with a corresponding Doppler interval having a Doppler length (TD) where a frequency function used for tentative Doppler shift compensation and represented by a step function (sine, cosine) is constant.

Abstract: A set of device parameters consisting of clock bias and position of a mobile device is determined without previous knowledge of the week number (WN) in that solutions of a set of equations derived from a least squares type weight function involving pseudoranges related to the device parameters via basic equations are attempted with a time of week (TOW) extracted from satellite signals and various week number candidates. A solution algorithm which iteratively solves the set of equations is used, each iteration step involving a linearization of the latter and resulting in corrections of the device parameters. After elimination of week numbers where the solution algorithm does not yield a solution a valid week number is selected from the remaining week numbers in that a deviation value is determined which reflects differential terms, i.e., differences between pseudorange values as measured and as derived from the set of device parameters according to the solution, e.g., by evaluation of the weight function.

Abstract: A mechanism for 1:1, 1+1, and UPSR path-switched protection switching, particularly for optical interface units in synchronous optical network (SONET) multiplexer equipment. A working unit and a standby unit pair protect each other in the event of a failure of the working unit or the failure of the span connected to the working unit if both the working and standby units are connected to different spans. Each unit is made responsible for detecting failures of the span that it receives and is primarily responsible for detecting a fault within the unit's own hardware or software. When a unit or span failure is detected, switch control is localized to the two units (i.e. the working and standby unit) which eliminates the need for a third control unit, which reduces processing time and reduces the system hardware.

Abstract: A float register spill cache method for improving the efficiency of usage of floating point single precision registers computer using a microprocessor conforming to the SPARC-V9 architecture specification. Values are temporarily stored in a plurality of double precision registers which are utilized as a float spill cache having a plurality of float spill slots. Values are generally shifted from one of the single precision registers to a second single precision register which is used as a spill pad, and then from the spill pad to a selected one of the float spill slots.

Abstract: A system and method of cleaning up a full erase unit in a flash translation layer, including moving all valid blocks on the full erase unit to a corresponding address location on a predetermined transfer unit, and then erasing the contents of the full erase unit. After erasure, the formerly full erase unit is redesignated to become the next transfer unit to which the contents of the next full unit will be transferred. The method also includes determining whether a criterion has been met for cleanup to be undertaken. The criteria for undertaking cleanup includes determining whether the number of free blocks is greater than a threshold which is a function of twice the number of bad blocks in the transfer erase unit plus twice the number of flash translation layer structure blocks in the full erase unit.

Abstract: A multilevel port system on a computer operating under a multilevel operating system to permit contemporaneously opening a plurality of sockets having the same port number while meeting the requirements of an appropriate security policy, thus allowing third party applications to run as if they were unimpeded by the security policy, and methods thereby. The computer system having an operating system adhering to an access control security mechanism. Such systems include government systems wherein a hierarchy of security classification levels are defined (e.g., top secret, secret, classified, unclassified), and commercial systems. Sensitivity labels pursuant to an access control security mechanism include at least hierarchical security classifications, and may include non-hierarchical categories or compartments which represent distinct areas of information in a system.

Abstract: A phase frequency detection circuit and method in a phase lock loop circuit uses delay circuits to limit the period of expression of up and down signals which adjust the output frequency of a voltage controlled oscillator. The pulse frequency detection circuit includes cross-linked latches to drive logic gates which produce output signals for adjusting the output frequency of a voltage controlled oscillator and delay circuitry connected to the outputs of particular logic gates for selective nullification of up and down control signals to a voltage controlled oscillator.

Abstract: An optical isolator system and method improving the manufacturability of the system, including fabricating a unitary tubular optical isolator system in two parts which are soldered together. The tubular system includes an internal disk to protect the isolator from heated solder during joinder of containment portions. The optical isolator system includes tubes to space polarizer, analyzer, and isolator portions.

Abstract: An imaging spectrometer that includes a mask (214) that has an array of n rows (302) and n columns (304) of transmissive elements (306) for transmitting the light from a plurality of locations of an image and of opaque elements (308) for blocking light from a plurality of locations of the image. The transmissive and opaque elements are arranged in a Hadamard pattern having rows (and columns) that are different cyclic iterations of an m-sequence. A grating (110) disperses the transmitted light from the transmissive elements (306) in a linear spatial relationship in a predetermined relationship to the wavelength of the transmitted light. A detector array (406) has a plurality of detector elements (408) arranged in a row to receive the dispersed transmitted light from the grating (110). Each detector element (408) provides an intensity signal indicative of the intensity of the light impinging thereon.

Abstract: An optical recording system writes data on an optical disk that has a user data area having a plurality of sectors and that has a map having first and second indicators corresponding to a portion of the plurality of sectors. The first indicator has a first logic state indicating that a corresponding sector contains data and has a second logic state indicating that the corresponding sector does not contain data. The second indicator has a first logic state indicating that the corresponding sector is to be erased. A recorder is coupled to the optical disk for erasing data and the indicators from the sectors and the map, respectively, in response to an erase command. The recorder writes data and the indicators on the sectors and the map, respectively, in response to a write command.

Abstract: A random access memory, having multi-bit memory cells, includes a successive approximation analog-to-digital (SAAD) converter and a comparator for reading data from the memory cells. In reading data from a cell, the SAAD generates a first reference voltage. This first reference voltage is compared, by the comparator, to the voltage stored in the cell to derive a first comparison result. Based on this first comparison result, a first bit of data is determined. Thereafter, the SAAD generates a second reference voltage based on the first reference voltage and the first comparison result. This second reference voltage is compared, by the comparator, to the voltage stored in the cell to derive a second comparison result. Based on this second comparison result, a second bit of data is determined.

Abstract: A memory has a plurality of memory cells that each store a voltage signal indicative of a multiple bit signal. Each logic value of the multiple bit signal has a unique voltage range. The voltage ranges are unequal and are selected so that the decay of the voltage of the voltage signal in the range remains in the range for each level at a predetermined time. This memory provides logic levels so that the decay time of the voltage signal is greater for larger voltages of the voltage signal. The decay time in each logic level is almost equal. A voltage generator provides the voltage signal to the memory cells responsive to a multiple bit digital data signal. The voltage generator may include a digital-to-analog converter that provides the voltage signal and has at least one more bit than the multiple bit digital data signal. A memory stores a lookup table and provides another multiple bit data signal to the digital-to-analog converter responsive to the multiple bit digital data signal.

Abstract: A display system displays a cursor on a monitor using parallel pixels of video data. A hardware cursor processor receives a sequence of clock signals, cursor data, parallel video data arranged in P logical pixels per clock signal, and cursor position data. The hardware cursor processor provides composite video data representative of the cursor data and the video data to a memory. The composite video data is arranged in P logical pixels per clock signal. The hardware cursor processor arranges the cursor data within the P logical pixels per clock signal in response to the cursor position data. The cursor position data includes a position signal HPOS indicative of the horizontal position of the cursor on the screen and includes a preset signal HPRE indicative of the horizontal offset of the cursor. The cursor data is arranged within the P logical pixels of the composite video data to begin at the logical pixel equal to [(HPOS-HPRE) modulus P].

Abstract: A slide component is configured to be inserted into a recess in an assembled magnetic diskette cartridge and rotated about an edge of the slide component into operable orientation to be slideably positioned between locations in the recess that designate whether or not the magnetic disk in the cartridge is write-protected.

Abstract: A random access memory, having multi-bit memory cells, includes a successive approximation analog-to-digital (SAAD) converter and a comparator for reading data from the memory cells. In reading data from a cell, the SAAD generates a first reference voltage. This first reference voltage is compared, by the comparator, to the voltage stored in the cell to derive a first comparison result. Based on this first comparison result, a first bit of data is determined. Thereafter, the SAAD generates a second reference voltage based on the first reference voltage and the first comparison result. This second reference voltage is compared, by the comparator, to the voltage stored in the cell to derive a second comparison result. Based on this second comparison result, a second bit of data is determined.

Abstract: A system and method for optimizing data transmission and storage of minimal sets of position, time, and residual information required for differential global positioning involving at least two GPS receiving stations, one of which may be stationary and at least one of which is mobile, with increased accuracy and compactness. The method includes sending or storing minimal and enhanced combinations of information. If the indicated values are stored rather than immediately transmitted, they may be retrieved for subsequent combination with values established at another station which may be stationary or mobile. The invention relates particularly to the enablement and performance of compacted storage and transmission of position-oriented and residual information for GPS systems and methods.

Abstract: A remote access granting system has a remote access requester that reads an identification code from a magnetic strip on a card and provides a sequence of request signals indicative of logical ones and zeros on separate conductors to a remote access interface. In response to the request signals, the remote access interface pulse modulates a DC voltage signal on a transmission line with a request pulse having a first pulsewidth indicative of a logical one or with a request pulse having a second pulsewidth indicative of a logical zero. A controller interface detects the pulse modulation on the DC voltage signal, demodulates the request pulses, and provides on separate conductors to a controller a first request pulse indicative of a logical one and a second request pulse indicative of a logical zero. The controller determines whether the sequence of request pulses matches a predetermined sequence.

Abstract: In a magnetic recording system, an asymmetry detector reverses the phase of a read, single-frequency test signal to indicate to a micro-controller whether recording signal asymmetry is present. Upon detecting such asymmetry, the micro-controller causes a current source coupled to the recording head to adjust a write current to correct the timing of a written data signal.