Abstract: A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region curvature correction may be obtained by using two MOS transistors in the pad driver/buffer and operating the transistors so as to proportionately increase output impedance of one of them when the output impedance of the other decreases, and vice versa. A linear pad impedance may be maintained over a range of Vpad values, while also maintaining the Vgs supplied to pad driver transistors at its maximum possible value to obtain greater linearity.

Abstract: The present disclosure is directed to an apparatus and method for producing and comparing signals from various points in a MEMS device. By producing signals which should be of substantial identical characteristics, deviations from the situation where the signals are of identical characteristics can be used to identify various types of asymmetry which are otherwise difficult to detect. In one embodiment, the MEMS device is comprised of a plurality of fixed beams arranged symmetrically and a plurality of movable beams arranged symmetrically. A first sensor is formed by certain of the fixed and movable beams while a second sensor, electrically isolated from said first sensor, is formed by at least certain other of the fixed and movable beams. The first and second sensors are located within the MEMS device so as to produce signals of substantially identical characteristics. A circuit is responsive to the first and second sensors for comparing the signals produced by the first and second sensors.

Abstract: A rotatable micro-machine is comprised of a solvent reservoir, a porous evaporation region and a channel connecting the solvent reservoir to the evaporation region. The evaporation region may be constructed of capillary paths that enable a capillary action which pulls solvent from the channel so as to enable a flow of solvent from the reservoir to the evaporation region through the channel. A rotatable member has portions in communication with the channel so as to be rotated by the flow. In one embodiment, the rotatable member may be a component of a micro-turbine generator. A system may be comprised of the rotatable micro-machine in combination with at least one electrical circuit. The porous region may be positioned to receive heat from the circuit.

Abstract: A method and apparatus for storing and using “register use” information to determine when a register is being used for the last time so that power savings may be achieved is disclosed. The register use information may take the form of “last read” information for a particular register. The last read information may be used to force the value of the register, after being read, to zero or to clock only that register while masking off the other registers. Several methods and hardware variations are disclosed for using the register use information to achieve power savings.

Abstract: The present invention relates to a characterizing a timing delay curve of a circuit component, said timing delay curve having a first region and a second region. The method includes determining a first delay equation representing the first region of the delay curve, determining a second delay equation representing the second region of the delay curve, and determining a corner capacitance representing a transition point from the first region to the second region.

Abstract: The disclosed system and method significantly reduce or eliminate DQS postamble ringing problem in modern high-speed memory chips, allowing the memory chips to be operated at significantly faster clock speeds. The external strobe signal (XDQS) may be used to generate at least two derivative strobe signals therefrom. Instead of the XDQS signal, the derivative strobe signals are then used, in a predetermined order, to clock in or strobe the data to be written into memory cells. The last generated derivative strobe signal may be used to finally transfer the data bits into memory cells. Once the last of the derivative strobe signals is activated, and so long as there are no more data writes pending in the command pipe for the next clock cycle, the rising or falling edge of the last derivative strobe signal can be detected to turn off further generation of the strobe signals prior to any onset of postamble ringing on the XDQS signal.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock (generated at the output of the delay line). A delayed version of the feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line.

Abstract: A mobile device for traversing a ferromagnetic surface. The device includes a frame and at least one surface contacting device attached to the frame. The device also includes a Halbach magnet array attached to the frame, wherein the Halbach magnet array provides a magnetic force to maintain the surface contacting device substantially into contact with the ferromagnetic surface.

Abstract: Each of a plurality of speaklets (MEMS membranes) produces a stream of clicks (discrete pulses of acoustic energy) that are summed to generate the desired soundwave. The speaklets are selected to be energized based on the value of a digital signal. The greater the significance of the bit of the digital signal, the more speaklets that are energized in response to that bit. Thus, a time-varying sound level is generated by time-varying the number of speaklets emitting clicks. Louder sound is generated by increasing the number of speaklets emitting clicks. The present invention represents a substantial advance over the prior art in that sound is generated directly from a digital signal without the need to convert the digital signal first to an analog signal for driving a diaphragm.

Abstract: Methods of operating a memory device comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory cells. One method comprises outputting an n-bit word in two ½n bit prefetch steps from a plurality of memory arrays in response to an address bit. Another method comprises prefetching a first portion of a word from a memory array, and prefetching a second portion of the word from the memory array, the first and second portions being determined by an address bit. Another method comprises reading a word from a memory array in at least two prefetch operations, wherein the order of the prefetch operations is controlled by an address bit.

Abstract: An apparatus enables the reordering of a block of n-bit words output from a plurality of memory cells according to information in certain address bits before outputting at least one n-bit word from a memory device while ignoring those certain address bits before inputting at least one n-bit word into the plurality of memory cells. The apparatus may additionally comprise examining at least two of the least significant bits of a column address and wherein the reordering is responsive to the examining. Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA0–CA2 identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA0–CA2 being “don't care” bits assumed to be 000.

Abstract: A reduced order model called the Fundamental Mistuning Model (FMM) accurately predicts vibratory response of a bladed disk system. The FMM software may describe the normal modes and natural frequencies of a mistuned bladed disk using only its tuned system frequencies and the frequency mistuning of each blade/disk sector (i.e., the sector frequencies). The FMM system identification methods—basic and advanced FMM ID methods—use the normal (i.e., mistuned) modes and natural frequencies of the mistuned bladed disk to determine sector frequencies as well as tuned system frequencies. FMM may predict how much the bladed disk will vibrate under the operating (rotating) conditions. Field calibration and testing of the blades may be performed using traveling wave analysis and FMM ID methods. The FMM model can be generated completely from experimental data. Because of FMM's simplicity, no special interfaces are required for FMM to be compatible with a finite element model.

Abstract: The method of the present invention is to modify an initial target distribution it ? by combining it with a point mass concentrated on an “artificial atom” ? which is outside the state-space X. A Markov chain may then be constructed using any known technique (for example, using the Metropolis-Hastings Algorithm) with the new target distribution. For this chain, the state ? is Harris-recurrent (i.e. with probability one, it occurs infinitely many times). By the Markov property, the times at which the new chain hits ? are regeneration times. To recover an ergodic chain with limiting distribution ?, it is sufficient simply to delete every occurrence of the state ? from the new chain. The points immediately after the (deleted) occurrences of the state ? are then regeneration times in a Markov chain with limiting distribution ?.

Abstract: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock.

Abstract: The present invention describes a processes that builds an acoustic cavity, a chamber, and vent openings for acoustically connecting the chamber with the acoustic cavity. The dry etch processes may include reactive ion etches, which include traditional parallel plate RIE dry etch processes, advanced deep and inductively coupled plasma RIE processes. Three embodiments for connecting the chamber to the cavity from the top side of the substrate, e.g. by using pilot openings formed using at least a portion of the mesh as an etch mask, by forming the vent openings using at least a portion of the mesh as an etch mask, or by having the chamber intersect the vent openings as the chamber is being formed, illustrate how the disclosed process may be modified. By forming the cavity on the back side of the substrate, the depth of the vent holes is decreased. Additionally, using at least a portion of the micro-machined mesh as an etch mask for the vent holes makes the process self-aligning.

Abstract: The present invention determines that an object is moving within a scene. At run time, the number of primitives used to represent the moving object is reduced. The degree of reduction can be related to the amount of motion, i.e. speed, of the moving object. The moving object is then rendered based on the reduced number of primitives saving time and memory bandwidth.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: A method of boosting the voltage supplied to an output pad driver through a bus connected to a voltage regulator. The method comprises momentarily connecting the bus directly to a voltage source and temporarily enabling the voltage regulator to source additional current to an output terminal thereof. A method of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, the gate voltages supplied by a voltage regulator through an output bus. The method comprises periodically determining the demand for gate voltage and, when the demand is high, momentarily connecting each line of the bus to a voltage source, and temporarily enabling the voltage regulator to source additional current to an output terminal thereof.

Abstract: A CMOS bandgap reference (BGR) voltage generator circuit has a passive resistor T-network of low resistance connected between the inverting and non-inverting inputs of the op-amp in the circuit. The op-amp's output is connected to the gates of three PMOS transistors and the drains of two of the transistors are connected in a looped manner to the input terminals of the op-amp. The T-network is placed between these drains that connect to the op-amp.