Abstract: A method and circuit is provided for creating multiple product lines from a single silicon implementation of an integrated circuit (IC). Specifically, logic blocks within the IC are selectively disabled after manufacturing the IC to create various ICs of different functionality from a single silicon implementation of the IC. In one embodiment, a first logic block of the IC is coupled to a disable circuit by a first disable line and a second logic block of the IC is coupled to the disable circuit by a second disable line. The disable circuit can disable the first logic block by driving the first disable line to a disable logic state. Similarly, the disable circuit can disable the second logic block by driving the second disable circuit to the disable logic state. In an FPGA embodiment of the present invention, the first logic block is a row of configurable logic blocks (CLBs) and the second logic block is a column of CLBs.

Abstract: A programmable logic device (PLD) includes a plurality of logic resources, a plurality of multi-bit configuration memories (MBCMs), and a trigger logic structure. The plurality of MBCMs include multiple memory slices that allow the PLD to switch rapidly between configurations, or contexts. In one embodiment, at least one memory slice configures the PLD into a logic analysis context for providing on-chip testing. In one embodiment, the plurality of logic resources include a plurality of storage elements. State data generated by a user-defined context is stored in the plurality of storage elements. When the trigger logic structure provides a trigger signal, the PLD is reconfigured into the logic analysis context. The logic analysis context reads and processes the state data stored in the plurality of storage elements to test the performance of the user-defined context.

Abstract: A variable clock divider circuit is provided. The variable clock divider circuit receives an input clock signal and generates an output clock signal having an output clock frequency that is less than the input clock frequency of the input clock signal. In one embodiment, a controller generates a rising-edge control signal and a falling-edge control signal. An output generator drives rising edges on the output clock signal in response to active edges on the rising-edge control signal. Conversely, the output generator drives falling edges on the output clock signal in response to active edges on the falling-edge control signal. The frequency of the rising-edge control signal and the frequency of the falling-edge control signal are variable. Common settings for the frequency of the rising-edge control signal and the falling-edge control signal include the frequency of the input clock signal divided by an integer.

Abstract: An FPGA includes an embedded non-volatile memory coupled to a configuration access port. The configuration access port allows the non-volatile memory to program the configuration memory of the FPGA. On power-on or reset, the non-volatile memory configures a first portion of the FPGA using configuration data stored in the non-volatile memory. Other portions of the FPGA can also be configured using the embedded non-volatile memory. Alternatively, an external configuration device can configure the other portions of the FPGA through a configuration port. Further, either the embedded non-volatile memory or the external configuration device can reconfigure the first portion of the FPGA.