Abstract: An integrated circuit package includes an integrated circuit die having a circuit surface and a back surface opposite the circuit surface. A layer of ductile material is deposited on the back surface of the integrated circuit die.

Abstract: A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y1. A path slack for a hold timing check is calculated from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y2. The path slack calculated for the setup timing check and for the hold timing check is generated as output.

Abstract: An apparatus includes an edge expose unit for exposing an annular area in an edge exclusion zone of a wafer to radiation having a wavelength suitable for removing a film from the wafer in the annular area and a radiation modulator coupled to the edge expose unit for modulating the radiation to pattern the film in the annular area.

Abstract: A method of isolating sources of variance in parametric data includes steps of: (a) cleaning a data set of measurements for a plurality of parameters; (b) generating a principal component analysis basis from the cleaned data set; (c) estimating an independent component analysis model from the principal component analysis basis; (d) calculating percentages of variance for the plurality of parameters explained by each component in the estimated independent component analysis model; (e) if the calculated percentages of variance indicate that a component is a minor component, then transferring control to step (f), else transferring control to step (g); (f) removing the minor component from the principal component analysis basis and transferring control to step (c); and (g) generating as output the estimated independent component analysis model wherein no component of the independent component analysis model is a minor component.

Abstract: A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.

Abstract: A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the corrected mask design to find a critical edge of a polygon that is closer than a selected minimum distance from a polygon edge opposite the critical edge, constructing a critical region bounded by the critical edge and the polygon edge opposite the critical edge, comparing the critical region to a potential defect criterion, and generating as output a location of the critical region when the critical region satisfies the potential defect criterion.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: A method and sample for radiation microscopy include a sample source that includes an area of interest, an outer side of a sample formed in the sample source adjacent to the area of interest, an inner side of the sample formed inside the sample source wherein at least a portion of the area of interest is included between the inner side of the sample and the outer side, and a particle beam channel formed inside the sample source for conducting a particle beam to or from the inner side of the sample.

Abstract: The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher frequency operations may be embedded as diffused blocks within the lower layers or may be programmed from a configurable transistor fabric above the diffused layers. Preferably the power mesh is located above the layers having the operations requiring the different frequencies, and may be fixed in an application set given to a chip designer or may be configurable by the designer her/himself. For example, to support high speed communications adjacent an embedded high speed data transceiver, the transistor fabric may be programmed as a data link layer having higher performance requirements than the rest of the integrated circuit.

Abstract: A method of placing and routing an integrated circuit design includes generating an initial placement and routing for at least a portion of an integrated circuit design. The initial placement and routing of the integrated circuit design is analyzed to find a critical location and is partitioned into a series of nested shells. Each shell surrounds the critical location and each preceding shell. An ordering of the shells and at least one of a timing constraint and an area constraint are selected for each shell. Each shell is placed and routed in the order selected according to the timing constraint and area constraint.

Abstract: A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchronous clock domains in the integrated circuit design; and (c) if a path between synchronous clock domains is defined as a false path in the integrated circuit design, then reporting a fatal violation.

Abstract: A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input an integrated circuit design that includes at least a portion of a block for placement and routing on a substrate and an outer boundary of the block. An end cell is selected from a set of end cells for terminating the block in an outer area that extends from the outer boundary to an end cell boundary outside the block. The selected end cell is placed in the outer area to isolate the block electrically from the substrate.

Abstract: A scan chain partition includes a serial input coupled to a scan input signal pin of a module under test. A plurality of scan sub-chains is coupled to the serial input. A scan sub-chain output multiplexer is coupled to the plurality of scan sub-chains for sequentially selecting only one of the scan sub-chains in response to a scan sub-chain control signal. A scan sub-chain controller generates the scan sub-chain control signal and gates a scan clock signal to only a scan clock input of the selected scan sub-chain.

Abstract: A method and firmware for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit includes steps of receiving as input timing information for an integrated circuit design including at least one metal layer and a plurality of signal wires and dummy metal wires in the metal layer, finding at least one of a setup time and a hold time for each signal wire in the metal layer from the timing information, identifying a timing-critical signal wire from at least one of the setup time and the hold time for one of the signal wires that would produce a timing violation in the signal wire when the signal wire is shorted to a dummy metal wire by a process defect in the metal layer, calculating at least one of a wire width, a fracture interval, and a spacing for modifying the dummy metal wire to avoid the timing violation in the timing-critical signal wire, and generating as output at least one of the wire width and the fracture interval for the dummy metal wire.

Abstract: A electronic design automation tool, apparatus, method, and program product by which design requirements for an intended semiconductor product and the resource definitions of a semiconductor platform are input. From the design requirements and the resource definitions, parameters specific to clocking are derived, e.g., clock property information, clock domain crossing information, and clock relationship specification. The tool and method embodied therein validates the clocking parameters of the design requirements with the resource definitions and invokes errors if the parameters are not realizable. Once the desired clocking parameters are consistent with the actual clocking parameters, correct physical optimization constraints and timing constraints are generated for the clocks. An iterative process can achieve correct and minimal clocking constraints.

Abstract: A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing analysis tool that includes a timing check for a path having a start point at an input of the critical structure and an end point at an output of the critical structure.

Abstract: A method of routing an integrated circuit design includes steps of receiving as input at least a portion of an integrated circuit design including at least two separate routing rules assigned to the same net for routing the integrated circuit design, formulating a single combined routing rule as a function of content of each of the separate routing rules, and generating as output the combined routing rule and a routing rule assignment that assigns the combined routing rule to the net.

Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.

Abstract: A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; calculating a separate interconnect delay for the interconnect as a function of an input ramptime for each of the inputs; adding a gate delay of each of the inputs to the separate interconnect delay calculated as a function of the input ramptime to estimate a stage delay for each of the inputs; and generating as output the stage delay for each of the inputs.

Abstract: An apparatus includes a register of an integrated circuit for shifting a scan test pattern in response to a scan enable signal. The register includes: a shift input for receiving the scan test pattern; a system logic input for receiving a system logic signal; a clock input for receiving a next clock pulse; a scan enable input for switching the register between a shift mode and a normal mode; a register output for latching the shift input in the shift mode or the system logic input in the normal mode in response to the next clock pulse; and a scan enable gating circuit coupled to the scan enable input for holding the register in the shift mode while the scan enable signal is in the shift mode and immediately following a transition of the scan enable signal from the shift mode to the normal mode until after the register output has latched the shift input in response to the next clock pulse following the transition of the scan enable signal to the normal mode.