Abstract: The bit rate control goals for applications using storage devices with the capability to process a variable bit rate data stream differ from the constant bit rate case. Therefore the encoder control strategy is adapted to this situation. For the first e.g. 80% of the total playing time an average bit rate is produced which is e.g. 95% only of the normal average bit rate. For the remaining 20% of the playing time the value for the desired average bit rate ascends to e.g. 150% of the normal value. During the first 80% the virtual buffer size is increased by a factor of e.g. 100 whereas during the last 20% the virtual buffer size descends to the normal value. Thereby an increased decoding quality can be achieved during e.g. 80% of the playing time. In the remaining playing time there is nearly no loss in the normal decoding quality.

Abstract: The present invention belongs to the field of transmission of a signal, using OFDM modulation (Orthogonal Frequency Division Multiplexing), from a transmitter to at least one receiver, via a transmission channel. The invention relates in particular to a device and a method for equalization of the received OFDM signal. Said equalization device is fitted into the reception system between a synchronization module and a module for binary decoding of the received signal, in which the receiver includes a recursive vector equalizer (10) capable of correcting the received signal in the time domain.According to the invention, the recursive vector equalizer (10) includes computation means (16; 22; 24; 40; 44; 46; 56) capable of estimating each transmitted symbol as a function of an estimate of the transmitted symbol which precedes the said transmitted symbol.

Abstract: A digital compressed video signal transmission system includes a transport processor for segmenting compressed MPEG video data into transport cells for transmission. A plurality of data fields in each transport cell are utilized to uniquely define transmitted data, provide system synchronization and to provide for detection of lost or corrupted data. These data fields include fields which indicate the service to which the data relates, the state of signal scrambling, a field identifying the one of several alternative formats in which the cell payload is arranged, a continuity count for determining data continuity, and a payload of either compressed video data or data auxiliary to the compressed video data.

Abstract: A circuit for developing a binary bitstream signal from a ternary analog signal having positive and negative amplitude peaks includes an analog-to-digital converter for receiving the analog signal and providing digital samples in accordance with the amplitude and polarity of the analog signal. The most significant bit of digital sample indicates the polarity of an analog signal sample. A threshold value is compared to a current amplitude sample to indicate a level change in the analog signal when the sample value exceeds the threshold value and the polarity differs from that of the preceding sample which exceeded the threshold value. The current sample value which exceeds the threshold value is compared with preceding sample values which exceeded the threshold value, and a level change is indicated by the sample value which most exceeds the threshold value. Incorrect sample values are inverted in a correction circuit.

Abstract: A variable length decoder including the cascade combination of a buffer memory for providing parallel-bit coded data in N-bit bytes, and a first barrel shifter having an R-bit input port and an R-bit output port (R>N). The R-bit output port of the first barrel shifter is coupled to respective first inputs of a bank of R two-input OR gates. The outputs of the OR gates are coupled to the parallel input of a register or latch, the output of which is coupled to the address input port of a lookup table for providing decoded versions of variable length codewords applied to its address port, and providing indicia which indicates the length of respective decoded variable length codewords. The output of the register is also coupled to the input of a second R-bit input R-bit output second barrel shifter. The output of the second barrel shifter is coupled to respective second input connections of said bank of OR gates.