Abstract: A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.

Abstract: A BiCMOS integrated circuit is formed with CMOS transistors on an SOI substrate in a silicon layer having a standard thickness of 0.1 &mgr;m to 0.2 &mgr;m and with Bipolar SiGe transistors formed in an epitaxial layer nominally 0.5 &mgr;m thick. The CMOS transistors are formed first with standard processing, then covered with an insulating film. The insulating film is stripped in the bipolar areas and an epitaxial SiGe layer is deposited on the Si substrate. The bipolar transistors are formed using the SiGe epi layer for the base and having an encapsulated structure for device isolation using shallow isolation trenches and the buried oxide.

Abstract: A process of forming a wiring in a semiconductor interlayer dielectric, include simultaneously patterning a via and a slotted line in the interlayer diectric, simultaneously etching the via and the slotted line, and simultaneously filling the via and the slotted line with a metal.

Abstract: A copper-interconnect, low-K dielectric integrated circuit has reduced corrosion of the interconnect when the crackstop next to the kerf is also used as the primacy barrier to oxygen diffusion through the dielectric, with corresponding elements of the crackstop being constructed simultaneously with the circuit interconnect elements; e.g. horizontal interconnect elements have a corresponding structure in the crackstop and vias between interconnect layers have corresponding structures in the crackstop.

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports.

Abstract: A method of forming an integrated circuit having four thicknesses of gate oxide in four sets of active areas by: oxidizing the silicon substrate to form an initial oxide having a thickness appropriate for a desired threshold voltage transistor; depositing a blocking mask to leave a first and fourth set of active areas exposed; implanting the first and fourth set of active areas with a dose of growth-altering ions, thereby making the first set of active areas more or less resistant to oxidation and simultaneously making the fourth set of active areas susceptible to accelerated oxidation; stripping the blocking mask; forming a second blocking mask to leave the first and second sets of active areas exposed; stripping the initial oxide in exposed active areas; stripping the second blocking mask; surface cleaning the wafer; and oxidizing the substrate in a second oxidation step such that a standard oxide thickness is formed in the second set of active areas, whereby an oxide thickness of more or less than the stan

Abstract: The present invention discloses at least one source metal that is embedded in at least one inert material to form a stand-alone structure and process thereof. It is preferred that the source metal is nickel or alloy thereof, and the inert material is at least one ceramic.

Abstract: In a particle beam lithography system, focus adjustment is controlled by a measurement of the gap between the workpiece being processed and a reference surface, such as the bottom surface of the focus lens, using a pair of capacitive sensors mounted on an arm that rotates to place one sensor on the beam axis to measure the workpiece height and the other displaced from the beam aperture to measure the height of the reference surface. The sum of the two readings is constant (for a given gap dimension), so that the accuracy of the measurement is not affected by the position of the arm within the gap.

Abstract: The difficulty of etching noble metals in ferroelectric capacitors is eliminated by a damascene process that employs chemical-mechanical polishing to remove the unwanted material, resulting in a lower electrode formed in an aperture in a dielectric, having a flat central portion and a wall extending from the central portion to the top surface of the surrounding dielectric; and an upper electrode formed in a two-level aperture, so that the upper electrode structure has a flat central portion, a first vertical wall extending from the central portion to a rim surrounding the central portion and extending over the wall of the lower electrode, and a second vertical wall extending from the rim to the top surface of a surrounding dielectric.

Abstract: A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask register receives a corresponding mask bit for each received data bit, each mask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. The mask register is preferably set to a masked state. Un masking occurs when an enable signal is asserted on a bit by bit basis. This allows the remaining bits within the burst length to be in a masked state when a write burst interrupt command is asserted.

Abstract: A BiCMOS integrated circuit is formed with CMOS transistors on an SOI substrate in a silicon layer having a standard thickness of 0.1 &mgr;m to 0.2 &mgr;m and with Bipolar SiGe transistors formed in an epitaxial layer nominally 0.5 &mgr;m thick. The CMOS transistors are formed first with standard processing, then covered with an insulating film. The insulating film is stripped in the bipolar areas and an epitaxial SiGe layer is deposited on the Si substrate. The bipolar transistors are formed using the SiGe epi layer for the base and having an encapsulated structure for device isolation using shallow isolation trenches and the buried oxide.

Abstract: A negative wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage (2 v)) and one driver circuit in each group is exposed to a boosted wordline high voltage (2.8 v) greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard nfet in series with a high threshold voltage pfet, so that, during activation, the unselected driver circuits exposed to the boosted wordline high voltage have a very low leakage through the pfet, while the selected driver circuit has a high but tolerable leakage (2 &mgr;A) because Vqs on the nfet is nearly at the nfet threshold.

Abstract: A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.

Abstract: A method and structure for manufacturing an integrated circuit device includes forming a storage device in a substrate, lithographically forming a gate opening in the substrate over the storage device, forming first spacers in the gate opening, forming a strap opening in the substrate using the first spacers to align the strap opening, forming second spacers in the strap opening, forming an isolation opening in the substrate using the second spacers to align the isolation opening, filling the isolation opening with an isolation material, removing the first spacers and a portion of the second spacers to form a step in the gate opening, (wherein the second spacers comprise at least one conductive strap electrically connected to the storage device) forming a first diffusion region in the substrate adjacent the conductive strap, forming a gate insulator layer over the substrate and the step, forming a gate conductor over a portion of the gate insulator layer above the step, forming a second diffusion region in th

Abstract: A pulse Doppler, laser radar as described which includes master laser whose output Fo is shifted in frequency by dF(t) during its amplification. The dF(t) frequency shift is compensated by providing a modulator which modulates the master laser output frequency Fo with a local oscillator signal F1. A first mixer is provided which combines the shifted master laser frequency signal and the local oscillator modulated, master laser output so as to eliminate the master laser frequency Fo from the combined signals. A second mixer is provided for combining the reflected, Doppler shifted laser signal with the local oscillator modulated, master laser output signal Fo +F1 to eliminate the master laser output frequency Fo from the combined signal. Additional detection circuitry is provided to determine the difference in frequencies of the combined signals from the first and second mixers so as to isolate the Doppler shift signal from the amplifier-induced shift dF(t).

Abstract: GaAs films compensated with TEOV to reduce free electron concentration are grown having superior morphology by heating the TEOV above the temperature used in the prior art, filtering the other constituents but not the TEOV, and reducing the arsenic ambient during the preliminary heating phase.

Abstract: A sampling device operating as a buffer between a first data signal and a relatively slow processing device accepts the input signal and stores samples of it on a SAW traveling past an input electrode. A blocking potential is applied to a set of electrodes to store a set of charge packets with the SAW device. Packets are consecutively released at a slower rate accommodated to the needs of the next processing unit in line, to read out the sampled signal at a modified rate for intentional distortion of the input signal, for slowing the output stored signal rate, or for time reversal of the signal.

Abstract: A high speed analog to digital converter system employs a set of ACT devices in parallel to buffer a high speed data sampling rate to the processing rate of the analog to digital converters employed. Vernier control of phase between individual devices is maintained by controlling the speed of propagation of the SAW wave by illumination of the substrate in response to a phase comparison between the SAW and a reference signal.

Abstract: A semiconductor optical head structure for accessing storage locations on an optical storage medium, such as an optical disk, for writing, erasing, and reading of information, including tracking-error detection and focusing-error detection systems is taught. Both error detection systems are optically and electrically separated to avoid any mutual inter- ference of the error signals, and all optical elements of the optical head are integrated on one chip. The focusing-error signal is generated by deflecting a separate beam (20A) out of an optical head and focusing it onto the surface of an optical disk and detecting the reflected portion thereof. The separate readout and tracking-error signal is generated by employing a light beam which is focused on the center of the pits of a track and detecting the diffracted portion thereof. Focusing-errors can be reduced by actuating the head perpendicular to the disk using a coil.

Abstract: A detector for laser radiation that detects the presence of above-threshold radiation in one of a set of wavelength ranges employs a set of Fresnel lenses designed to focus radiation in a particular band onto a metal-coated film. A series of Fresnel lenses is designed with constant focal lengths, but each lens is designed to have that focal length at a specific wavelength. Only when the wavelength of the incident radiation matches the design wavelength of the Fresnel lens will the film be marked or machined. Radiation of differing wavelengths will be defocused to a degree that will reduce the intensity below the level that will mark or machine the film. An electronic based version of this spectroscopy detector can also be implemented.