Abstract: A method for designating a subvocabulary for speech recognition systems includes the steps of providing a vocabulary of words each having a flag with a first value, selecting words to be eliminated from the vocabulary, setting the flags of the selected words to a second value and processing speech based on words having the flag set to the first value. A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for disabling and enabling of subvocabularies in speech recognition systems, the method steps include providing a vocabulary of words each having a flag with a first value, selecting words to be eliminated from the vocabulary, setting the flags of the selected words to a second value and processing speech based on words having the flag set to the first value.

Abstract: An impedance control circuit designed to match the impedance between a semiconductor device and a transmission medium (PCB) by using a current source installed in the semiconductor device instead of using an external resistor is provided. Since the impedance control circuit does not use an external resistor for impedance matching, the PCB size can be reduced. In particular, a controllable current source matches the impedance more precisely compared to the external resistor.

Abstract: A method for forming an oxide layer on a silicon substrate includes forming a sacrificial oxide layer on the silicon substrate, implanting nitrogen into the silicon substrate, annealing the silicon substrate having implanted nitrogen, removing the sacrificial oxide layer from the silicon substrate, and forming an oxide layer on the silicon substrate. The dose of nitrogen implanted into silicon is preferably higher than 1e14 cm31 2. The annealing process is preferably performed at temperatures in a range from about 550° C. to about 1000° C. and for a time period between about 1 second and about 2 hours.

Abstract: A method for providing voice confirmations corresponding to actions of passengers in a vehicle includes the step of detecting an action performed by an occupant of the vehicle. A corresponding voice confirmation is identified from among a plurality of pre-stored voice confirmations. The corresponding voice confirmation is audibly reproduced. The reproducing step may include the step of synthesizing the corresponding voice confirmation, or the step of playing back a pre-recorded voice confirmation as representative of the corresponding voice confirmation.

Abstract: A three-dimensional color ultrasonic encoding and/or decoding system is provided in which a three-dimensional color ultrasonic image is classified into zero pixel data, gray pixel data and indexed color pixel data, to thereby perform encoding and decoding based on the classification data. The encoding and/or decoding system includes an encoding system including a classifier, a first encoder for encoding gray pixel data and a second encoder for encoding indexed color pixel data, a run-level encoder, a pixel separator and a multiplexer, and a decoding system including a demultiplexer, a run-level decoder, a first decoder for decoding gray pixel data, a second decoder for decoding indexed color pixel data and an image mixer.

Abstract: A system and method for caching objects using a cost-based publish and subscribe paradigm, wherein a server computing node determines whether a given cache node should receive a cache update based on, e.g., the cost of sending the update. In one aspect, a method for maintaining objects in a cache comprises the steps of issuing a subscription for an object, maintaining a metric for the object; and determining, based on the metric, whether a cache is to receive an update message associated with the object. The metric is preferably correlated with one or more factors such as an importance factor of maintaining the cached copy of the object current, the cost of the sending the update message, and/or the estimated lifetime of the object.

Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.

Abstract: In a graphics system for a graphical user interface in which a plurality of screen objects are displayed, a method of targeting a screen object comprises determining a screen object targeted by a pointer and reading a pointer selection and selecting a targeted scream object. The method being characterized by generating, according to the proximity of the pointer position to a screen object, a weighting associated with each screen object, the weighting being in inverse proportion to the displayed size of the associated screen object; and wherein the determination is adapted to determine the targeted screen object according to the respective weightings associated with the scream objects.

Abstract: A handwriting recognition system and method whereby various character sequences (which are typically “slurred” together when handwritten) are each modelled as a single character (“compound character model”) so as to provide increased decoding accuracy for slurred handwritten character sequences. In one aspect of the present invention, a method for generating a handwriting recognition system having compound character models comprises the steps of: providing an initial handwriting recognition system having individual character models; collecting and labelling a set of handwriting data; aligning the labelled set of handwriting data; generating compound character data using the aligned handwriting data; and retraining the initial recognition system with the compound character data to generate a new recognition system having compound character models.

Abstract: A microprocessor capable of functioning in an expanded address mode is disclosed, including: a control unit for determining whether an external instruction is to be used for a normal address mode or to be used for an expanded address mode and for generating control signals; a program counter for generating a first address in response to an output from the control unit during the normal and expanded address modes; an address generator for generating a second address during the expanded address mode, in response to an output from the control unit; an address bus for transferring the first address out of the microprocessor; and a data bus for transferring the second address out of the microprocessor. The microprocessor also includes an address interface circuit for transferring the second address out of the microprocessor through the data bus.

Abstract: Disclosed is a method of protecting semiconductor areas while exposing a gate for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma layer of a silicon compound, selected from the group silicon oxide and silicon nitride, in a manner effective in leaving an upper surface of said gate exposed. Also disclosed is a method of processing short gates while protecting long gates on a semiconductor surface, the method comprising depositing a planarizing layer of a silicon compound, selected from the group silicon nitride and silicon oxide, up to substantially the same height as said gates, and processing said semiconductor surface.

Abstract: Apparatus and methods for packaging and dispensing coiled material. A device for packaging a coil of metallic ribbon stock comprises a first planar panel and a second planar panel, wherein the first and second planar panels have substantially the same shape, and a sidewall panel that interconnects the first and second planar panels along the perimeter of the first and second planar panels to form a container. The sidewall panel comprises preferably comprises a plurality of perforated regions each defining an aperture through which a roller is inserted to rotatably engage a coil of metallic ribbon stock within the container.

Abstract: A digital signal processing system performs different word-length arithmetic operations (e.g., 24-bit arithmetic and 16-bit arithmetic) using the same hardware. The digital signal processing system includes internal buses, a host processor coupled to the internal buses, a DSP coprocessor coupled to the internal buses for performing a digital signal processing under control of the host processor, and first and second data memories coupled to the internal buses. The DSP coprocessor further includes a random access memory (RAM) pointer for generating addresses to access the first and second data memories, a multiply and accumulate (MAC) unit for performing a multiply and accumulate operation, an arithmetic unit, a shift and exponent unit for shifting operands and for evaluating exponents, and a local decoder for decoding DSP commands from the host processor and controlling the RAM pointer, the arithmetic unit, and the shift and exponent unit.

Abstract: A method for registration of magnetic resonance (MR) and computed topography (CT) images, in accordance with the present invention includes providing MR images having a region of interest delineated by first contours and providing CT images having the region of interest delineated by second contours. A pre-existing model of the region of interest is also provided. The pre-existing model is fit to the first contours or the second contours to provide a first resultant model. The first resultant model is then copied to provide a copied model. The copied model is fit to the other of the first contours and the second contours to provide a second resultant model. By rotating and translating the first resultant model and the second resultant model, the first resultant model and the second resultant model are registered.

Abstract: A semiconductor memory device is provided in which a burst length and/or a column address strobe (CAS) latency may be fixed. The semiconductor memory device, which may be an SDRAM (synchronous dynamic random access memory) device, includes a memory cell array, a burst address generation circuit to generate a burst address and a burst length detection signal, a mode setting register for setting a CAS latency and/or a burst length using an address, a pipeline circuit to delay and output data read from the memory cell array. The semiconductor memory device also includes a latency enable control signal generation circuit to generate a latency enable control signal in response to a read command or signal and the burst length detection signal, and a data output circuit to output data being output from the pipeline circuit in response to the latency enable control signal. Therefore, a circuit configuration is simplified and a test time is reduced, by fixing latency and/or burst length.

Abstract: An object of the present invention is to level out variations in output voltage levels caused by the difference in the characteristics of the output amplifiers of a source driver, and to reduce vertical streak noise on the display screen. A source driver 12 for a liquid crystal panel according to the present invention comprises output amplifier switching means 10 for switching an output amplifier 80, which amplifies analog signal converted from digital image signal by the digital/analog converter 82 and provides the converted analog signal to source lines 74 of a liquid crystal panel 70, to another output amplifier at regular time intervals.

Abstract: A semiconductor device is provided for controlling entry to and exit from a power down (DPD) mode of a semiconductor memory comprising; a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and biasing circuitry for biasing a plurality of nodes of at least one of the plurality of voltage generators to at least one predetermined voltage potential to prevent false triggering of circuits upon entry/exit of DPD mode.

Abstract: Disclosed is a data processing system comprising a control unit for receiving data from a main core and outputting given control signals, a level shifter for amplifying the electric potential of said given control signals and outputting corresponding driving signals, a data output buffer for receiving said driving signals from said level shifter and outputting a driving voltage having a voltage range defined in the PCI or/and PCI-X specifications, to an input/output pad, and said data output buffer being in a high impedance state to prevent a PCI mode voltage inputted to said pad from being leaked to a power source terminal when said data processing system is operated in PCI mode.

Abstract: The present invention involves a method for generating a partial Cyclic Redundancy Checking (CRC) value of a first interval of data in a digital data stream. The method includes the step of loading a precomputed CRC value corresponding to a one bit followed by a predetermined number of zeros. The predetermined number of zeros correspond to the number of digits of a polynomial minus one. The first interval of data is partitioned into a plurality of bits. The precomputed CRC value corresponding to the one bit followed by the predetermined number of zeros is enabled, for each of the plurality of bits having a value of one. The enabled, precomputed CRC values are combined to generate the partial CRC value of the first interval of data. Advantageously, multiple copies of the process may be executed in parallel to achieve a large speed-up.

Abstract: A testcase management system comprises a test suite including a plurality of testcases, wherein these testcases are cooperable with a test harness for executing a test run in which at least one of the testcases is executed on a system to be tested. A method and apparatus are provided for generating a list (overall list) indicative of the testcases that are to be executed during the test run. The overall list is generated as follows: A list is generated of all testcases in the test suite. Some of these testcases will have been fully tested in all environments and be verified as approved. They are manually added to an approved list. Others are disapproved and are manually added to a disapproved list. A list is automatically generated comprising those testcases which are neither approved nor disapproved. They are not-tested. Those testcases on the disapproved and not-tested lists are excluded from the overall list.