Abstract: An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division calculations with cost effective comparator operations. The method also includes improved image sharpening when up-sampling an image.

Abstract: As part of a process for producing a structured ASIC that is functionally equivalent to an FPGA that has been programmed to perform a user's logic design, a compilation of that design that has been prepared for ASIC implementation is converted to a physical layout of the structured ASIC. The production of this physical layout honors timing constraints supplied by the user, and also preserves functional equivalence to the reference programmed FPGA. The structured ASIC can be manufactured from the physical layout produced.

Abstract: Programmable logic device circuitry for receiving and/or transmitting a differential signal includes controllable invert circuitry that effectively reverses the polarity of the differential signal. The controllable invert circuitry operates on a single-ended (non-differential) signal that has either been derived from a differential input signal or from which a differential output signal will be derived.

Abstract: Disclosed herein are systems, methods and apparatus, for detection and identification of analytes in a volatilized or volatilizable sample, using the mobility-based signature that is produced when the volatilized sample is passed through an ion mobility based analyzer.

Abstract: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A quantum cryptography system [100] may include a transmitter [110] configured to generate entangled first and second photons, modulate and detect the first photon, and transmit detection information and the second photon. The system [100] may also include a receiver [160] configured to modulate the second photon. The receiver [160] may also be configured to detect the second photon based on the detection information.

Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

Abstract: Methods and apparatus for classifying or predicting the classes for samples based on gene expression are described. Also described are methods and apparatus for ascertaining or discovering new, previously unknown classes based on gene expression.

Abstract: Possible deficiencies of a communication link are detected and automatically counteracted, at least to some degree. The deficiencies addressed can include phase shift and attenuation compensation. The counter-action can include adjustment of pre-emphasis given a signal applied to the communication link and/or adjustment of equalization given a signal received from the communication link.

Abstract: A data converter for a padded protocol interface performs, on a first data sample, decoding operations requiring data from second and third data samples, while buffering the second data sample without buffering the third data sample. A state machine controlling the decoding operation waits an additional clock cycle, until the second sample has become the current sample and the third sample has become the second sample and thus is available.

Abstract: A system and method can detect and track targets in a scene of interest. Interframe differencing can be performed on sequential pairs of images of the scene and a Bayesian model analyzer can obtain an interframe difference density function. The interframe difference density function can be partitioned into static and mobile regimes to provide an objective function. A tracking module can construct a level set and geodesic active contours can be determined for the targets. An adaptive control can apply a spatial transformation and level set perturbation to the geodesic contours to oscillate the contours such that the level set can drop to a lower energy level. The expanded contour can be fed back for use in processing subsequent interframe differences. Target motion analysis data, such as bearing and bearing rate data, can be extracted from the geodesic active contours by applying geometric based transformations on the curve's coordinates.

Abstract: Digital compressed codes, associated with advertisements enable a user to selectively record additional information, which would be broadcast on a television channel at a later time. The advertisement could be print advertisement or broadcast advertisement on television or radio. The user enters the digital code (I code) associated with an advertisement into a unit with a decoding means which automatically converts the code into CTL (channel, time and length). The unit within a twenty four hour period activates a VCR to record information on the television channel at the right time for the proper length of time. The decoded channel, time and length information can be communicated directly to a VCR and used by the VCR directly to automatically activate the VCR to record a given television information broadcast corresponding to the communicated channel, time and length.

Abstract: Programmable logic devices, such as field programmable gate arrays, may have input/output (I/O) circuitry that can be programmed for either differential or single-ended signaling. I/O pins coupled to such programmable I/O circuitry typically have high parasitic input pin capacitance during differential signaling. I/O pins may also have high parasitic input pin inductance. Additional impedance circuit elements such as capacitive or inductive devices are coupled in the programmable I/O circuitry to produce a compensatory impedance that reduces, if not substantially eliminates, the effects of the parasitic input pin capacitance and/or inductance during differential signaling.

Abstract: A system for implanting an implant and method thereof is disclosed. In general overview, the system includes an implant, an envelope enclosing the implant, a delivery assembly and an attachment piece for attaching the envelope or implant to the delivery assembly. The envelope may include a drug coating, positioning aids, and means to ease envelope removal. In one embodiment, the delivery assembly is employed for implant and/or envelope delivery inside the patient's body. In another embodiment, the delivery assembly and an attachment piece are employed to deliver the implant or the envelope inside the patient's body.