Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements.

Abstract: Methods and apparatus, including computer program products, implementing techniques for compositing a digital image. The invention performs the steps of providing a current accumulation image; identifying as the current element of the digital image to be processed a graphics element having a backdrop property, the backdrop property identifying a backdrop image into which the element is to be blended; using the element and the backdrop image to create a modified backdrop image; obtaining a shape mask for the element; and crossfading the current accumulation image with the modified backdrop image using the shape mask. The result of the crossfading becomes the current accumulation image for any further compositing.