Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.

Abstract: Circuitry in an integrated circuit for programming an antifuse element is disclosed. In one embodiment, oscillating voltages are produced at two nodes, and these voltages are approximately 180.degree. out of phase with one another. In another embodiment, an oscillating voltage is produced at one node and a negative voltage is produced at a second node. In each embodiment, the maximum difference in voltage between the two nodes is sufficient to program an antifuse element.

Abstract: A chalcogenide memory cell with chalcogenide electrodes positioned on both sides of the active chalcogenide region of the memory cell. The chalcogenide memory cell includes upper and lower chalcogenide electrodes with a dielectric layer positioned therebetween. The dielectric layer includes an opening defining a pore. A volume of chalcogenide material formed integral to the upper chalcogenide electrode is contained within the pore. The upper and lower chalcogenide electrodes both have greater cross sectional areas than the pore.

Abstract: An integrated circuit semiconductor device includes a charge pump to provide current at a potential which is greater than a supply potential. The charge pump utilizes an oscillator, which causes the charge pump to cycle, and thereby provide a continuous output at an elevated potential. In order to optimize efficiency of the charge pump, the oscillator is able to change its frequency in response to output potential. In the preferred embodiments, this is accomplished by selectively inserting a supplemental portion into a ring oscillator loop. When used with an integrated circuit device, such as a DRAM, the current from the charge pump may be supplied to nodes on isolation devices and nodes on word lines, thereby improving the performance of the DRAM without substantially changing the circuit configuration of the DRAM array.

Abstract: A vertical transistor semiconductor and method of making a vertical transistor is provided. The vertical transistor is particularly suited for use in a DRAM cell. The structure permits a DRAM cell to be fabricated with a comparatively low number of masking layers. Moreover, the vertical nature of the transistor allows a larger number of transistors per surface area compared to conventional techniques. The method and apparatus also utilizes a buried digit line. The digit line may include a portion that is a metal material that in a preferred embodiment is step-shaped sidewall of the digit line. The transistor is particular suited for use with a variety of DRAM capacitors.

Abstract: There is described a memory cell having a vertically oriented polysilicon pillar diode for use in delivering large current flow through a variable resistance material memory element. The pillar diode comprises a plurality of polysilicon layers disposed in a vertical stack between a wordline and digitline. The memory element is disposed in series with the diode, also between the wordline and the digitline. The diode is capable of delivering the large current flow required to program the memory element without also requiring the surface space on the upper surface of the memory matrix normally associated with such powerful diodes. The invention allows memory cells to be disposed every 0.7 microns or less across the face of a memory matrix. Further, the memory cell is easily fabricated using standard processing techniques. The unique layout of the inventive memory cell allows fabrication with as few as three mask steps or less.

Abstract: Apparatus is disclosed for disabling the charge pumps in an integrated circuit memory when data is being read from the memory.

Abstract: A fluid separation system is disclosed for installation within a wellbore that penetrates a production formation and a discharge formation. The system comprises a first pump and a second pump each operatively connected to a means for operation, such as a downhole electric motor, and a fluid separator for separating wellbore fluids from the production formation into a first stream and a lighter second stream. Wellbore fluids are introduced into the first pump, and are then conveyed to an inlet of the fluid separator. The second stream exiting the fluid separator is conveyed to an inlet of the second pump, and from the second pump to the earth's surface. Devices are included, such as wellbore packers, to isolate the discharge formation from the production formation, so that the second stream exiting the fluid separator directly enters the discharge formation.

Abstract: A rolling cutter drill bit comprises a body and three legs, each leg having a cantilevered bearing spindle, a rolling cutter rotatably mounted on the bearing spindle, lubricant delivering means within the beating spindle, and a floating thrust bearing element configured to carry onward thrust loads from the rolling cutter onto the bearing spindle. Each floating thrust bearing element is formed of a wrought alloy material consisting primarily of chromium carbide and cobalt and having a yield strength of less than 120,000 psi and a ductility of at least 4%, both at room temperature.

Abstract: A field emitter display having reduced surface leakage comprising at least one emitter tip surrounded by a dielectric region. The dielectric region is formed of a composite of insulative layers, at least one of which has fins extending toward the emitter tip. A conductive gate, for extracting electrons from the emitter tip, is disposed superjacent the dielectric region. The fins increase the length of the path that leaked electrical charge travels before impacting the gate.

Abstract: An integrated circuit semiconductor device includes a charge pump to provide current at a potential which is greater than a supply potential. The charge pump utilizes an oscillator, which causes the charge pump to cycle, and thereby provide a continuous output at an elevated potential. In order to optimize efficiency of the charge pump, the oscillator is able to change its frequency in response to output potential. In the preferred embodiments, this is accomplished by selectively inserting a supplemental portion into a ring oscillator loop. When used with an integrated circuit device, such as a DRAM, the current from the charge pump may be supplied to nodes on isolation devices and nodes on word lines, thereby improving the performance of the DRAM without substantially changing the circuit configuration of the DRAM array.

Abstract: A selective etching and chemical mechanical planarization process is employed for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays. The process is employed to construct an emission grid whereby the gate structure is capable of producing a field strength at the cathode tip sufficient to generate electron emission. The gate is disposed at a location above the tip such that the gate physically intercepts the outermost lateral portions of the beam, yet does not induce a significant electrostatic outward divergence of the beam, thereby reducing the cross-section of the beam.

Abstract: A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages. The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock. Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages. Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge. The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal. Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode. In a method of use, a first stepped voltage is developed on a first capacitor and selectively coupled to a second capacitor to develop a second stepped voltage of greater absolute value.

Abstract: A method for chemical vapor deposition onto high aspect ratio features. Process gases including a reactant species are supplied to the surface and sufficient primary energy is supplied to the surface so as to cause the reactant species to deposit on the surface. Additional energy is supplied, preferably in the form of optical energy, that is tuned to be captured by the patterned features so as to slow the deposition rate preferentially on the patterned features.

Abstract: A device and a method of forming a floating gate memory transistor of very small area, thereby allowing a high-density integrated circuit chip, more specifically for Erasable Programmable Read-Only Memory (EPROM) or similar non-volatile devices.In a first embodiment, a method is disclosed that fabricates a programmable memory cell described as a "diffusion cut" cell where a plug-type floating gate contact hole cuts through a diffusion region and partially into a substrate region. In a second embodiment, a method is disclosed that fabricates a programmable memory cell described as an "oxide cut" cell, where the plug-type floating gate contact hole only penetrates a silicon oxide layer. This "oxide cut" cell is formed in a similar fashion except penetration does not go into the diffusion region or substrate.