Abstract: A method is disclosed wherein the voltage of a semiconducting substrate can be locally pumped to a voltage different than the bulk of the semiconducting substrate generally. The local voltage may be pumped into a localized portion of the bulk substrate, or it may be pumped into a portion of the substrate that is isolated from the bulk substrate. This localized biasing may be used for various purposes, including the adjustment of body effect in a plurality of transistors, adjusting the threshold voltage of a capacitor, and reducing latch-up sensitivity of a transistor circuit.

Abstract: A method and apparatus for encapsulating a BGA package. Specifically, the molded packaging material is configured to provide cups on the backside of the package, opposite the semiconductor device. The cups expose pads on the substrate and are configured to receive solder balls.

Abstract: A system for providing a signal indicating whether a process is installed and providing improved voltage regulation. A contact is selected and isolated from an array of ground contacts and is further coupled with circuit for generating an INSTALL signal. A capacitor and pull up resistor coupled to a supply voltage, ground and the isolated contact form a signal line at a common node such that a circuit to ground is completed through the processor and the isolated contact when the processor is plugged in and a direct signal indication of the presence or absence of the processor is provided. Voltage sense lines of a Voltage Regulation Module (VRM) are coupled directly to processor contacts isolated from an existing voltage supply contacts coupled to the supply plane of a supply voltage within the circuit board providing improved regulation without adversely affecting power supply current capacity considerations.

Abstract: A technique for generating replacement values for defective pixels in a digital imaging system includes generating a base values for the defective pixels and a statistical characterizing values which provide consistent statistical relationships with other pixels. The base values may be computed as mean values of pixels surrounding the defective pixels. The statistical characterizing values may be selected to provide deviation from the mean values by a standard deviation of other selected pixels, such as pixels in the neighborhoods of the defective pixels. The technique avoids image artifacts due to inconsistent noise or other statistical characteristics in the pixel replacement values.

Abstract: A protective assembly for electronic components. The protective assembly has a base and a first printed circuit board secured to the base. An electronic component is disposed on the printed circuit board and protected by a rigid member that is also secured to the base. The protective assembly is designed to be mechanically and electrically coupleable to a computer-based system.

Abstract: A technique is disclosed for shielding rf magnetic fields in MRI systems. An rf shield is embedded in a gradient coil structure including X-, Y- and Z-axis coils. The rf shield is positioned between an inner gradient coil which is inherently decoupled from the rf field, and the remaining coils which require rf shielding. The inner gradient coil may be a Z-axis coil wound as a solenoid, the field of which is generally orthogonal with respect to the rf magnetic field. The rf shield is thereby placed at an enhanced distance from the rf coil, providing greater efficiency and permitting energy levels to be reduced to obtain the desired rf magnetic field strength.

Abstract: A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack comprising one or more thin film layers covers the gate oxide layer. A gate electrode pattern is partially etched into the gate stack, the partial etching step being completed before any of the gate oxide layer is exposed. Sidewall spacers are formed on edge surfaces of the partially formed gate electrode. Source and drain regions are created by ion implantation using the partially etched gate electrode and the sidewall spacers as a mask. The sidewall spacers are removed and lightly doped drain regions are formed by ion implantation using the partially etched gate electrode as a mask.

Abstract: A technique is provided for verifying network connectivity between a medical diagnostic system and a remote service facility. The remote service facility is contactable at will by the subscribing system to request service, information, technical assistance, and so forth, while the service facility may also contact the subscribing system for acquisition of data, transmission of service messages, protocols, and so forth. In the connectivity verification sequence, a subscribing system is selected by the service facility and a network connection is established. A message is transmitted to the system provoking software at the system to re-establish the network connection from the system side. Two-way connectivity is thereby verified. Mobile systems may be configured to contact the service facility at their own initiation, and exchange data for permitting the service facility to re-contact the mobile system.

Abstract: A technique is described for detecting defects such as short circuits in a device such as a discrete pixel detector used in a digital x-ray system. The technique employs test circuits associated with each row driver of the detector. The test circuits are enabled by a test enable input signal, and the row driver sequentially enables the rows of the detector, along with the individual test circuits. In a test sequence, output signals from the row test circuits are monitored to identify whether a defect, such as a short circuit, is likely to exist in the row or row driver. The test circuitry adds only minimal area and complexity to the row driver function, providing a high degree of test coverage at a low cost, with minimal likelihood of test circuitry-induced failures.

Abstract: A method for fabricating chalcogenide memories in which ultra-small pores are formed in insulative layers using disposable spacers. The chalcogenide memory elements are positioned within the ultra-small pores. The chalcogenide memory elements thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms.

Abstract: A high voltage electrical connection between a base unit and a panel display in a portable computer wherein the base unit and the panel display are pivotably secured to each other about a hinge axis, includes a flexible high voltage electrical conductor extending from the base unit to the panel display. A portion of the electrical conductor extends along the hinge axis such that pivoting of the panel display relative to the base unit causes said portion of the flexible conductor to twist about the hinge axis rather than actively bend.

Abstract: An FBGA packaged device including a die adhered to a substrate with a small gap being formed between the die and substrate. An opening is formed through the substrate adjacent the center portion of the die. An encapsulating mold is formed around the die extending into the gap and also filling the channel. At least one barrier is disposed in the gap between the substrate and the die adjacent the channel to control the flow path of the encapsulating material as the mold is formed in the package.

Abstract: A technique for shifting the phase of a periodic signal. A periodic signal, such as a clock signal, may be provided in a synchronous system, such as a memory system implementing a Synchronous Dynamic Random Access Memory (SDRAM) device. It may be advantageous to be able to phase shift the signal. The present technique implements a delay line which includes a plurality of delay elements coupled in series. The periodic signal is delivered to the delay line and the time between transitions from high to low or low to high is stored in one of a number of latches coupled to the delay line at various points. A number of tapping elements are also coupled to the delay line at some incremental point corresponding to a correlative latch. By varying the proximity of each tapping element and corresponding latch along the delay line, various phase shifts of the periodic signal can be produced.

Abstract: An integrated regulator and flow meter assembly having a piston reciprocatingly disposed in an opening of a body member, a support member disposed in the body member opening over the piston, and a flow tube coupled to the support member, wherein an aperture of the support member interconnects a flow conduit of the piston and the flow tube. A spring, preferably a wave spring or disc spring, biases the piston away from an orifice with a valve seat formed thereabout on an end portion of the body member opening. In one embodiment, the piston and a seating surface thereof are formed unitarily of a plastic material.

Abstract: An arrangement for utilizing a combustion sensor with an internal combustion engine. The arrangement includes a sensor mounted to the outside of an engine cylinder for communication with exhaust gasses within the cylinder via a sampling passage. A mounting structure holds the sensor proximate the sampling passage and forms a sensor chamber to receive exhaust gas therein. The sensor chamber includes a flow diverter to prevent remaining combustion particles and liquid droplets from lodging against the sensor. The chamber also includes a collection region for collecting the particles and liquid which can then be expunged through a drain outlet.

Abstract: An internal combustion engine that utilizes a control system for improving operation of the engine under a variety of conditions. The control system includes a sensor that directly senses a combustion condition in a cylinder. The output of the sensor is utilized in adjusting the air-fuel mixture delivered to other, non-sensed cylinders to optimize engine operation.

Abstract: The invention provides a cap for hermetically closing a receptacle having a retention flange, the cap being constituted by a lid surmounting a lateral skirt which is provided, in a bottom portion, with means for snap-fastening beneath said flange and in a top portion, with a removable tamperproofing strip occupying a fraction of the periphery of the skirt where it provides a temporary connection with said lid, and also providing a hinge in its complementary fraction; the cap being characterized in that said lid carries a locking tab whose free end is provided with a retractable catch suitable for coming into abutment against the flange of the receptacle in the fully-open position.

Abstract: A releasable packer has a control line therethrough. A hydraulic release mechanism of the packer is controlled from the surface by application of flow and pressure. A modification of the packer and release mechanism using resettable collets and return springs allows multiple sets and releases of the packer.

Abstract: An engine system having a low EMI/RFI signature. The system comprises a two-stroke engine having a cylinder with a piston sized for reciprocal motion through the cylinder. The two-stroke engine further includes an injector deployed in communication with the combustion chamber to discharge a fuel into the combustion chamber. An electronic control unit controls the injection and ignition for the engine, and an EMI/RFI reduction system is utilized to lower the electromagnetic and radio frequency interference signature of the engine.

Abstract: In a computer system having at least one host processor, a method and apparatus for providing seamless hooking and interception of selected entrypoints includes finding the IDT for each CPU which can include scanning the HAL image for the HAL PCR list. Saving the interrupt handler currently mapped in the CPU's interrupt descriptor table. Patching the original interrupt into the new interrupt handler. Storing the new interrupt exception into the CPU's interrupt descriptor table. Hooking a select entrypoint by first determining if the entrypoint begins with a one byte instruction code. If it does, saving the address of the original entrypoint, saving the original first one byte instruction, and patching the new interrupt intercept routine to jump to the original entrypoint's next instruction.