Abstract: A circuit for providing a carry operation utilizing 3-input look up tables 502 and 504 and subsequent logic, the circuitry being configurable to provide an adder, a subtractor, an up/down counter, a pre-loadable counter, an accumulator, and a wide gate such as a large AND gate. To provide a carry out Ci+1, a multiplexer 506 has a first input receiving a carry in Ci, a select input coupled to the output of look up table 502, and a second input coupled to the output of look up table 504. The look up tables receive signals representing numbers Ai and Bi to be added or subtracted and ADD/SUB indicating if addition or subtraction is desired. The look up table 502 is programmed to provide Ai(+)Bi, while look up table 504 is programmed to provide Ai*Bi, (+) indicating a Boolean exclusive OR, and * a Boolean AND. With ADD selected, multiplexer 506 provides the carry out Ci+1 of the operation Ai+Bi+Ci.

Abstract: A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions.