Abstract: A parallel SCSI host adapter integrated circuit includes a memory containing a table having a plurality of entries. Each entry in the plurality of entries is a parameter used in a data transfer over a SCSI bus to a target device. A target identification register stores a pointer to the table. A SCSI transfer parameter register is coupled to the memory. An entry in the table pointed to by the value stored in the target identification register is loaded into the SCSI transfer parameter register. Another SCSI transfer parameter register also is coupled to the memory so that another entry stored in the table is loaded into the another SCSI transfer parameter register. A decoder circuit connected to the a SCSI transfer parameter register has a set SCSI attention signal output line, an enable SCSI asynchronous transfer output line, and a reset SCSI attention signal output line.

Abstract: The transfer of multiple sectors of data between a hard disk drive and a computer data bus of a host computer is controlled by hardware within a computer bus interface circuit of a storage controller integrated circuit of this invention. Multiple sectors of data are transferred without intervention of a microprocessor that controls the operation of the disk drive containing the storage controller integrated circuit. The computer bus interface circuit of this invention not only automatically transfers data between the computer data bus and the computer bus interface circuit but also generates status information, generates interrupts to the host computer, and updates task file registers.

Abstract: A peripheral coupled to a SCSI bus is isolated using a SCAM isolation step and the original SCSI identification bits (32 bytes) are read from the isolated peripheral into a host adapter. The host adapter then generates a relatively small number (for example, 4 bytes) of identification bits from the relatively large number of original SCSI identification bits. The small number of SCSI identification bits is stored in a non-volatile memory of the host adapter such that the memory location of the SCSI identification bits of a particular peripheral corresponds with the logical system identifier of that peripheral. Even if peripherals are removed from the bus and/or added to the bus, the small number of SCSI identification bits for a peripheral previously on the bus is redetermined and located in non-volatile memory of the host adapter so that the logical system identifier of the peripheral previously coupled to the bus is not changed.

Abstract: A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. The control gate formed over the floating gate controls the portion of the channel region between the floating gate and the source to provide split gate operation. The source region is formed sufficiently far from the floating gate so that the channel length between the source region and the closest edge of the floating gate is controlled by the control gate but does not have to be accurately defined.

Abstract: A circuit calculates the exact biased resultant exponent before calculating the resultant mantissa of a division operation. The circuit includes a carry-save adder, a conditional-sum adder, a multiplexer and a comparator. The conventional carry-save adder receives the biased exponent of the dividend (e1), the one's complement of the biased exponent of the divisor (˜e2), and the bias. The conditional-sum adder receives the sum and carry resultants of the carry-save adder, outputting {er0=e1+(˜e2)+bias} and {er1=e1+(˜e2)+bias+1}. The comparator controls the multiplexer to respectively select as the resultant exponent either er0 or er1 when the fraction of the dividend is less than or greater than or equal to the fraction of the divisor. A circuit for determining the resultant exponent of a squareroot operation includes a conditional-sum adder, a multiplexer and a selection logic circuit.