Abstract: A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.

Abstract: A mechanism is provided for linking with source code, code commentary relating to the source code's execution. An advantage is achieved by storing the code commentary received from a user during software debugging about a program's execution directly alongside the source code.

Abstract: A method, system, and computer program product are provided for communicating to a powered element in a rack system. A controller injects communication data onto power lines that provides power to a plurality of powered elements. The powered elements determine if the communication data transmitted via the power lines should be used for configuration using an address embedded within the communication data. The powered elements compare an embedded target address within the communication data to the address of the particular element. If there is a match between the addresses, the corresponding powered element processes the communication data to configure the powered element. As a result, data may be communicated over the power lines thereby eliminating the need for separate communication lines. Thus, the amount of cables required to interconnect the powered elements of the distributed data processing system may be reduced by eliminating the communication lines from the system configuration.

Abstract: In accordance with one embodiment, a plurality of empirical measurements of a fabricated integrated circuit including a fabricated transistor having multiple terminals is received. The plurality of empirical measurements each include an empirical terminal current set and an empirical terminal voltage set for the terminals of the fabricated transistor. A mathematical simulation model of a simulated transistor is also received. Utilizing the mathematical simulation model, an intermediate data set is calculated by determining, for each of a plurality of different terminal voltage sets, a simulated terminal current set and a simulated terminal charge set. A modeling tool processes the intermediate data set to obtain a time domain simulation model of the fabricated transistor that, for each of the plurality of empirical measurements, provides a simulated terminal charge set. The time domain simulation model is stored in a computer-readable data storage medium.

Abstract: In accordance with an aspect of the present invention, specifying a portion of a circuit design to be treated as untimed by static timing analysis is performed on the RTL design by means of an attribute annotation. The process is operable to map through to the Physical Design by correlating latches and chip-level nets. This allows the testing process to become closed-loop. Design and simulation time is also greatly reduced due to the accessibility of RTL design.

Abstract: A mechanism is provided for packet coalescing in virtual channels of a data processing system. A first processor bundles original data into a data packet to be transmitted to a destination processor, the original data comprising payload data and overhead data. The first processor transmits the data packet to a second processor along a path to the destination processor. The second processor determines if the second processor has additional payload data destined for the same destination processor. Responsive to the second processor having the additional payload data, the second processor unbundles the data packet, adds the additional payload data to the payload data, and rebundles the payload data along with the additional payload data and the overhead data into a rebundled data packet. Then the second processor transmits the rebundled data packet to at least one other processor along the path to the destination processor.

Abstract: A mechanism is provided for performing scalar operations using a SIMD data parallel execution unit. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using vector operations in a SIMD data parallel execution unit. The scalar operations are converted, such as by a static or dynamic compiler, into one or more vector load instructions and one or more vector computation instructions. In addition, control words may be generated to adjust the alignment of the scalar values for the scalar operation within the vector registers to which these scalar values are loaded using the vector load instructions. The alignment amounts for adjusting the scalar values within the vector registers may be statically or dynamically determined.

Abstract: A power reset module may reset an automatic shut-off module of a target device by momentarily disrupting power to the automatic shut-off module at a determined interval and automatically restoring power after a time period of up to two minutes. In multiple embodiments, the power reset module comprises an activation switch with an activation switch output coupled to a frequency module. The frequency module may output a frequency module signal on a determined interval via a frequency module output coupled with a reset module. The reset module momentarily transitions a reset switch to a reset state periodically at the determined interval for up to two minutes prior to automatically transitioning the reset switch to a non-reset state.

Abstract: Systems, methods and media for implementing logic in the arithmetic/logic unit of a processor are disclosed. More particularly, hardware is disclosed for computing logical operations with minimal hardware by organizing the execution unit such that the propagate and generate functions required for the adder can be used as a basis to implement the bitwise logical instructions. The result of these functions is computed before execution of the instruction by an execution macro in the arithmetic/logic unit.

Abstract: A method for controlling input and output of a virtualized computing platform is disclosed. The method can include creating a device interface definition, assigning an identifier to a paging device and configuring commands useable by a virtual input output server. The commands can be sent to the input output server and can be converted by the input output server into paging device commands. A hypervisor can assist in facilitating the communication configuration. Other embodiments are also disclosed.

Abstract: Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamiclock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.