Abstract: A method and system to use a standard cell function library to automatically configure gate array cells in an integrated circuit layout is provided. A standard cell netlist at the transistor level is compiled to list the transistors required in implementing the desired functions. Based on the netlist, gate array cells are restructured so that they can be inserted in locations designed for standard cells. The restructured gate array cells, which are made up of single poly and double poly structures, are strategically placed in a layout. Using the function net connectivity patterns from the standard cell function library, the gate array cells are connected to implement desired logic functions.

Abstract: A modem interface communicates data between a computer and a modem that is coupled to an external communication network. The modem interface includes a host interface for coupling to a host processor of the computer, an analog interface for coupling to the modem, and a digital signal processor for processing the data communicated with the modem and the host processor. A memory is coupled to the host interface, the digital signal processor and the analog interface. The analog interface provides clock signals and converts data between analog and digital for communicating between the memory and the modem. The analog interface provides an interrupt to the digital signal processor to control the transfer of data from the digital signal processor and the memory. The modem interface processes data at sampling rates while the host processor processes data at rates less than the sampling rate of the analog interface.

Abstract: A method and circuit to regulate a random waveform signal to ensure that the LED indicator driven by the waveform signal is visible to the human eye is provided. The method and circuit first determines whether there is a pulse occurring. If an on-going pulse is detected, the regulated waveform signal is driven HIGH for at least 8 clock cycles. If no on-going pulse is detected, the regulated waveform signal is driven LOW for at least 8 clock cycles.

Abstract: A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slots through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus.

Abstract: An apparatus and method for canceling system oscillations caused by acoustical coupling is provided. The invention can be implemented in a low voltage environment and as an integrated circuit. Audio voltage signals generated by a microphone are provided as input to a data/fax/voice modem. The data/fax/voice modem processes the audio voltage signals and outputs differential transmit voltage signals to a hybrid/daa circuit for converting to a two-wire (tip and ring) circuit before connecting to a communication device such as a land based telephone or a cellular radio. Audio voltage signals generated by the communication device are provided via a two-wire (tip and ring) circuit to the hybrid/daa circuit for converting into a four-wire circuit and then provided as input to the data/fax/voice modem as differential receive voltage signals.

Abstract: A method and apparatus to prevent invalid data from propagating into devices connected to a PCI tristate bus is provided. The method and apparatus utilize the PCI bus control signals to monitor the bus transaction's mode (e.g., as a bus target or as a bus master), type (e.g., read, write), and status (e.g., ongoing bus transaction). Using these information, control the opening and closing of a window gate hardware to allow valid data to propagate into a device connected to the PCI tristate bus and to prevent invalid data from propagating into the device.

Abstract: A computer system coupled to a network is disclosed which provides multiple paths for each serial input/output connection. In the receive mode, the current invention separates serial data frames which are composed of sub-functions/channels into sub-function data streams. The sub-function data streams can then be transferred out one at a time. In the transmit mode, the current invention forms data load patterns from the sub-function data streams. Each data load pattern is formed by selecting the appropriate binary bits from the sub-function data streams and arranging the binary bits selected in the sequence desired. The binary bits of each data load pattern are transmitted serially.

Abstract: A synchronized frequency hopping method and apparatus for use in a cellular communication system where the cellular communication systems has a plurality of cells and a plurality of frequencies available to be assigned to the cells. At predetermined times, cells in the system synchronously change or hop to a new frequency. The new frequency to which a cell hops to may be a function of the present frequency the cell is assigned. In addition, synchronized frequency hopping may occur at predetermined intervals and the pattern of hopping may periodically repeat. This technique limits the period of time a non-system source of interference may impair communications in any cell since the cell hops to different frequencies periodically.

Abstract: A computer system comprises a plurality of user computers interconnected through a public-switched telephone network and trunk lines, and also includes a plurality of Remote Data Processing Nodes (RDPNs) similarly connected to each other and to the user computers. A BBS station which is also coupled to the network receives test data from the user computers. Each user computer includes a test unit that includes a digital signal processor and an active control unit. The test unit has a dialing directory for connecting to various BBSs to test out the communication through a modem and the telephone network. Using the dialing directory, the test unit activates the modem to make a predetermined call through the telephone network to several of the RDPNs. The test unit collects survey, snapshot and real-time data packets in a predetermined data file which are communicated to the BBS station for debugging the system and determining the performance of the system.

Abstract: A sense amplifier circuit is incorporated within a computer system and utilizes a latch coupled to an equalizing transistor that operates in the triode region and initially equalizes the sense amplifier circuit data outputs, the latch subsequently develops a voltage difference in response to a control signal, deactivation of the control signal then turns off the equalizing transistor thereby allowing the latch circuit to lock the developed voltage differential to full-swing across the sense amplifier data outputs.

Abstract: A method and apparatus to prevent data from being corrupted prior to reaching the final destination is provided. The method and apparatus monitors the status of posted write transactions and transaction initiations. If it is determined that a posted write transaction is incomplete and there is a pending transaction initiation, a bus retry is requested for the pending transaction.

Abstract: A clock frequency multiplier with a rise detector flip-flop connected to a series of buffers having interspersed parallel output taps connected to a binary to Gray converter for providing real time rise status indications. The parallel tap outputs are connected to first, second and third multiplexers, to produce first and second fall outputs and a second rise output. The multiplexers are controlled by first, second and third corresponding tap circuits having hexadecimal inputs from a Gray to hexadecimal converter connected to the output of the binary to Gray converter through a flip-flop clocked by a second rise of the input clock signal.

Abstract: A mechanism to effectively retrieve residual data received from a serial data source is provided. As the shift register receives serial data from the serial data source, the activities and content of the shift register is monitored. Status bits are set to reflect the activities and content. These status bits are used to determine whether the shift register contains residual data and whether such residual data should be ignored the serial data received from the serial data source is output to a destination.

Abstract: A clock doubler circuit with duty cycle control includes an exclusive-OR, a toggle flip-flop, a plurality of control bit flip-flops, a primary delay element, a plurality of secondary delay elements, and a multiplexer. The toggle flip-flop has a clock input connected to an output of the exclusive-OR, and an inverted data output connected back to a data input of the toggle flip-flop and connected forward to an input of the primary delay element. An output of the primary delay element is connected to an input of the multiplexer and to individual inputs of the plurality of secondary delay elements which in turn, have outputs connected to other inputs of the multiplexer. A plurality of control bits generated, for example, by a computer program running on a host processor, are respectively provided to data inputs of the plurality of control bit flip-flops which in turn, have data outputs connected to select inputs of the multiplexer.

Abstract: The present invention is implemented in a peripheral component coupled to a peripheral component interconnect (PCI) bus. The peripheral component includes an internal device operating in an internal clock domain while the PCI bus operates in a PCI clock domain. The system of the present invention efficiently interfaces the internal device with the PCI bus. The present invention generates and couples a request for PCI bus ownership, originating from the internal device, to the PCI bus. The present invention then determines whether the PCI bus is idle or busy. Where the PCI bus is idle, a proceed signal is generated for the internal device. Where the PCI bus is busy, a do not proceed signal for the internal device is generated. Both the proceed and the do not proceed signals are synchronous to the internal clock domain. The PCI bus is acquired and a data transaction from the internal device is executed when the internal device receives the proceed signal.

Abstract: A communication interface unit (128) facilitates data word exchanges between a parallel driven bus (210) and a serial driven communication channel (136) by performing both parallel-to-serial and serial-to-parallel data conversion functions. A transmitter circuit (200) is included in the communication interface unit (128), which performs parallel-to-serial data conversion employing a multiplexer circuit (204) and control logic circuitry (208). The multiplexer circuit (204) concurrently receives a plurality of data bits of a data word being transferred, and the control logic circuitry (208) thereupon causes the plurality of data bits of the data word to be successively passed through the multiplexer circuit (204) so as to perform parallel-to-serial conversion. A receiver circuit (300) may also be included in the communication interface unit (128), which performs serial-to-parallel data conversion employing a plurality of flip-flops (304) and control logic circuitry (308).

Abstract: A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable.

Abstract: A system of ISA bus cards compatible with plug and play protocol stores common resource data in a plurality of programmable read only memories which are each installed on the individual bus cards. A random access memory is also provided on each one of the bus cards. In order to comply with the plug and play protocol, each of the random access memories is programmed independently from the read only memories with a unique identification that identifies the individual bus card. The separation of the storage location of the unique identification from the resource data common to all of the bus cards allows for mass production and programming of the read only memories, while still providing the unique identification for each bus card that is required by the plug and play protocol.

Abstract: A mechanism to allow dynamic configurations and/or diagnostic of a computer system from a remote location is provided. The computer system receives instruction codes of a program from a data source. When executed by the CPU, the instruction codes performs the necessary erase and program operations to embed a firmware program onto to the flash memory. The firmware program can be used for configurations or diagnostic purpose.

Abstract: An efficient request-reply protocol for a client-server communication and data processing model. Under the novel protocol, a client sends a Request to a server and awaits a Reply. If the Reply is not sent before expiration of a timeout period in the client, the client sends a second Request. The server provides a conditional Acknowledge if a second Request is received from the client. Thereafter, the client waits for the server to transmit a Reply without the client sending additional Requests. Under normal conditions, the inventive protocol performs as well as the best prior art protocol (the optimistic model), while under abnormal conditions, the inventive protocol performs better than the optimistic protocol and only slightly worse than the prior art pessimistic protocol. Since normal conditions should prevail for a substantially longer amount of time than abnormal conditions, the present invention provides better average performance than either prior art client-server protocol.