Patents Represented by Attorney Frank M. Linguiti
  • Patent number: 5996860
    Abstract: A novel fluid container system comprises a container having a port at an upper end through which port fluid is permitted to pass for emptying the container. A restricter is provided within the container for momentarily restricting fluid flow out of the port when the container is inverted, the restricter having a construction such that a restricted fluid flow is permitted through the port for a period of time when the container is inverted, after which period of time a substantially less restricted fluid flow is permitted through the port. A retainer retains the restricter in the vicinity of the port. The retainer is disposed on an inner surface of the upper end of the container and extends inwardly from the inner surface. The retainer can include a substantially horizontal arcuate member or a circular member.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: December 7, 1999
    Inventor: Kenneth A. Alley
  • Patent number: 5692318
    Abstract: A pair of improved golf shoes has an inner flange extending longitudinally along the inner side of the shoes and an outer flange extending longitudinally along the outer side of the shoes. The inner flanges and the outer flanges extend outwardly beyond the exterior surfaces of the uppers of the shoes. On one of the improved shoes the outer flange extends outwardly farther than the inner flange. On the other shoe, the inner and outer flanges extend substantially the same distance beyond the exterior surface of the upper. Heels having outwardly extending flanges are provided. One of the heels extends outwardly over substantially its entire outer edge. The flange of the other heel extends outwardly beyond the upper for only a portion of its inner edge and is flush with the upper for the remaining portion of its outer edge. A portion of the shoe disposed below the ball of the foot of the user is thicker than the region disposed below the heel of the user in order to balance the user.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: December 2, 1997
    Inventor: Joseph F. Aliano, Jr.
  • Patent number: 5472084
    Abstract: Briefly stated, the present invention comprises a piggyback golf bag for use in a riding golf cart having a golf cart attachment device for attaching the golf bag to the golf cart. The piggyback golf bag includes a first golf bag portion and a second golf bag portion. The first golf bag portion has an opening for receiving a golf club and a body portion for retaining a golf club. The second golf bag portion, which is separate from the first golf bag portion, also has an opening for receiving a golf club and a body portion for retaining a golf club. A golf bag attachment device is provided for detachably securing the first and second golf bag portions to each other.
    Type: Grant
    Filed: July 19, 1994
    Date of Patent: December 5, 1995
    Inventor: Joseph F. Aliano, Jr.
  • Patent number: 5245672
    Abstract: The system of the present invention applies self-organizing and/or supervd learning network methods to the problem of segmentation. The segmenter receives a visual field, implemented as a sliding window and distinguishes occurrences of complete characters from occurrences of parts of neighboring characters. Images of isolated whole characters are true objects and the opposite of true objects are anti-objects, centered on the space between two characters. The window is moved across a line of text producing a sequence of images and the segmentation system distinguishes true objects from anti-objects. Frames classified as anti-objects demarcate character boundaries, and frames classified as true objects represent detected character images. The system of the present invention may be a feedforward adaption using a symmetric triggering network. Inputs to the network are applied directly to the separate associative memories of the network.
    Type: Grant
    Filed: March 9, 1992
    Date of Patent: September 14, 1993
    Assignee: The United States of America as represented by the Secretary of Commerce
    Inventors: Charles L. Wilson, Michael D. Garris, Robert A. Wilkinson, Jr.
  • Patent number: 5242047
    Abstract: The conveyor system of the present invention provides an endless belt system in which roller assemblies are aligned side by side in rows beneath the upper surface of the endless belt. Each individual roller assembly is provided with a roller and an axis about which the roller rotates. The roller assemblies are disposed in support members by lowering them into a receiving region in the support members. The receiving region is adapted to removably receive the roller assembles when the roller assemblies are lowered into the receiving region at any angle within a ninety degree range to prevent jamming of the assembly during insertion. The support members rotationally immobilize and retain the axis of the roller assembly while simultaneously providing structural integrity to the conveyor system. The roller shaft is maintained within the support member both by gravity acting upon the roller assembly itself and by the weight of the belt resting upon the roller assembly.
    Type: Grant
    Filed: January 10, 1992
    Date of Patent: September 7, 1993
    Assignee: United Parcel of America Inc.
    Inventor: Henri Bonnet
  • Patent number: 5226893
    Abstract: A hypodermic syringe includes an elongate housing having rear and forward ends and a piston chamber which slidably supports the piston to define an innoculant storage space within the housing, a hollow needle supported by the plunger assembly and in communication with the storage space. The needle is extendable from the forward end of the housing and retractable into the housing during an injection stroke and a safety device is provided for preventing re-use of the syringe after completion of the injection stroke. The safety device includes an override chamber at the rear end of the housing and adjoining the piston chamber, the override chamber having a greater width than the piston chamber, and a displaceable diaphragm located at or adjacent the juncture of the piston and the override chambers to partition and seal the override chamber from the piston chamber, the diaphragm being displaced by the piston and the piston entering the override chamber at the end of the injection stroke.
    Type: Grant
    Filed: May 8, 1991
    Date of Patent: July 13, 1993
    Inventor: Edward R. J. Kayser
  • Patent number: 5225904
    Abstract: A full motion color digital video signal is compressed, formatted for transmission, recorded on compact disc media and decoded at conventional video frame rates. During compression, regions of a frame are individually analyzed to select optimum fill coding methods specific to each region. Region decoding time estimates are made to optimize compression thresholds. Region descriptive codes conveying the size and locations of the regions are grouped together in a first segment of a data stream. Region fill codes conveying pixel amplitude indications for the regions are grouped together according to fill code type and placed in other segments of the data stream. The data stream segments are individually variable length coded according to their respective statistical distributions and formatted to form data frames.
    Type: Grant
    Filed: December 4, 1991
    Date of Patent: July 6, 1993
    Assignee: Intel Corporation
    Inventors: Stuart J. Golin, Allen H. Simon, Brian Astle, John M. Keith
  • Patent number: 5220753
    Abstract: The safety vacuum shield of the present disclosure may be detachably secured to a hand held power tool for removing particulate materials while performing work upon a workpiece with the power tool. Applying the power tool to the workpiece generates turbulence which moves the particulate materials, including particles of the workpiece as well as the tool bit. The safety vacuum attachment includes a shield for containing the turbulence and the moving particulate materials within an interior region defined by the shield when the power tool is in use. A first opening through the shield permits the power tool to extend therethrough and into the interior region. A second opening through the shield permits a vacuum to be applied to the interior region for providing a vacuum slip stream to draw materials within the slip stream from the interior region by way of the second opening.
    Type: Grant
    Filed: June 3, 1992
    Date of Patent: June 22, 1993
    Inventor: Robert S. Whitman
  • Patent number: 5189636
    Abstract: A video signal processor includes cicuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit adders, each of which has a carry-in input terminal and a carry-out output terminal. The carry-out output terminal of one of the adders is selectively coupled, via an AND gate, to the carry-in input terminal of the other adder. The AND gate is controlled by the mode control signal. In the mode where the circuitry operates as two eight-bit adders, additional circuiry is included to detect output values which may exceed the zero to 255 range of valid values and to saturate these invalid values either at zero or 255.
    Type: Grant
    Filed: December 10, 1990
    Date of Patent: February 23, 1993
    Assignee: Intel Corporation
    Inventors: Michael F. Patti, Nicola J. Fedele, Kevin Harney, Allen H. Simon
  • Patent number: 5150019
    Abstract: An integrated circuit electronic grid device includes first and second metal layers wherein a layer of a dielectric medium is disposed between the metal layers. A third metal layer is disposed above the second metal layer and insulated from the second metal layer by another layer of a dielectric medium. The first and second metal layers are biased with respect to each other to cause a flow electrons from the first metal layer toward the second metal layer. The second metal layer is provided with a large plurality of holes adapted for permitting the flow of electrons to substantially pass therethrough and to travel toward the third metal layer. A fourth metal layer is disposed above the third metal layer to collect the electrons wherein the third metal layer is also provided with a large plurality of holes to permit the electrons to flow therethrough and continue toward the fourth metal layer.
    Type: Grant
    Filed: October 1, 1990
    Date of Patent: September 22, 1992
    Assignee: National Semiconductor Corp.
    Inventors: Michael E. Thomas, Kranti V. Anand, deceased
  • Patent number: 5148381
    Abstract: An interpolator array having a plurality of interpolator array cells is provided for receiving first and second input values to be interpolated and an interpolator weight term, to provide an interpolated output. A bit of each of the two input values to be interpolated is received by an interpolator array cell and applied to a selecting circuit within a cell of the interpolator array. Additionally, an interpolation weight bit of the interpolation weight term is applied to the selection circuit. The selecting circuit applies either the input bit of the first input value or the input bit of the second input value to an adder within the interpolator cell in accordance with the value of the interpolation weight bit. An interpolator array cell also receives a partial product input and a carry-in input and applies these additional inputs to the adder. The adder provides a partial product output and a carry-out in accordance with the applied inputs.
    Type: Grant
    Filed: February 7, 1991
    Date of Patent: September 15, 1992
    Assignee: Intel Corporation
    Inventor: David L. Sprague
  • Patent number: 5141437
    Abstract: Apparatus is provided for planning the design of a region and the positioning of objects in the region. A first layout having a first layout area is disposed in the region to represent placement of an object such as an article of furniture within the region in a pre-determined relationship with the region. A second layout having a second layout area is disposed in combination with the first layout to form a layout combination having a combined layout area. The combined layout area is adjusted in accordance with the dimensions of the object being represented. In order to adjust the combined layout area one layout may be disposed over a portion of the other layout. The combined area of the two layouts can be adjusted by adjusting the amount of area of one layout disposed over the other. Additionally, the combined area can be adjusted by folding or cutting at least one of the two layouts.
    Type: Grant
    Filed: January 23, 1991
    Date of Patent: August 25, 1992
    Inventor: Vinson G. Fowlkes, Jr.
  • Patent number: 5123078
    Abstract: An optical interconnect structure, formed on a substrate, optically interconnects optoelectronic transmitting and receiving devices. The optical interconnect structure includes optical interconnects each of which includes a core member constructed of a material having a first predetermined index of refraction. The ends of the core members are chemically bonded either to an optoelectronic device or a core member of another optical interconnect. A cladding layer surrounds each core member. Each end of a cladding layer proximate to an optoelectronic device is chemically bonded to that device. The cladding layer is formed of a material having a second predetermined index of refraction, the magnitude of which is less than the magnitude of the first predetermined index of refraction.
    Type: Grant
    Filed: November 9, 1990
    Date of Patent: June 16, 1992
    Assignee: National Semiconductor Corp.
    Inventor: Michael E. Thomas
  • Patent number: 5117125
    Abstract: A logic level control circuit prevents impact ionization in a CMOS integrated circuit. The substrate bias voltage of the CMOS integrated circuit is detected by the control circuit and a control signal is provided in response to the detected bias voltage. The bias voltage can be zero volts or negative five volts. If the bias voltage is zero volts, the control signal is a logic level one. If the bias voltage is negative five volts, the control signal is a logic level zero. The control signal is applied to the gate of at least one other controlled device on the integrated circuit for turning the controlled device on and off. The controlled device coupled to a further CMOS device and turning the controlled device on and off prevents impact ionization by allowing the controlled device to alternately divide a voltage level with the further CMOS device or be effectively removed from the circuit.
    Type: Grant
    Filed: November 19, 1990
    Date of Patent: May 26, 1992
    Assignee: National Semiconductor Corp.
    Inventor: Michael K. Mayes
  • Patent number: 5117276
    Abstract: A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.
    Type: Grant
    Filed: November 8, 1990
    Date of Patent: May 26, 1992
    Assignee: Fairchild Camera and Instrument Corp.
    Inventors: Michael E. Thomas, Jeffrey D. Chinn
  • Patent number: 5111276
    Abstract: There is disclosed a structure for self aligned and non-self aligned power and ground buses and interconnects for integrated circuits which are thicker than normal conductors. This enables them to withstand higher current densities without adverse electromigration effects. There is also disclosed a method for making such structures.
    Type: Grant
    Filed: November 19, 1990
    Date of Patent: May 5, 1992
    Assignee: National Semiconductor Corp.
    Inventors: Hemraj Hingarh, Andres D. Asuncion, Michael Thomas, Robert Brown
  • Patent number: 5111355
    Abstract: A thin film capacitor for use in an integrated circuit includes a lower plate disposed on the silicon substrate of the integrated circuit. The lower plate comprises a barrier layer of conductive material which prevents transport of silicon from the silicon substrate into a layer of dielectric material which is disposed between the lower plate and an upper plate. A portion of the barrier layer can be consumed and transferred into dielectric material by, for example, high temperature oxidation which generates a symmetric series capacitor with the dielectric layer. A layer comprising an oxide of the barrier layer material is formed between the barrier layer and the dielectric layer by consuming an upper portion of the barrier layer.
    Type: Grant
    Filed: September 13, 1990
    Date of Patent: May 5, 1992
    Assignee: National Semiconductor Corp.
    Inventors: Kranti V. Anand, Michael E. Thomas
  • Patent number: 5094972
    Abstract: An integrated circuit device is fabricated upon a semiconductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.
    Type: Grant
    Filed: June 14, 1990
    Date of Patent: March 10, 1992
    Assignee: National Semiconductor Corp.
    Inventors: John M. Pierce, Sung T. Ahn
  • Patent number: 5091048
    Abstract: The surface of a semiconductor wafer is planarized by disposing the wafer in a wafer plane and rotating the wafer within the wafer plane wherein the rotation is around an axis perpendicular to the plane. A stream of particles is transported to the surface of the wafer while the wafer is rotating wherein the angle between the stream of particles and the wafer plane is small. The stream of particles mills the surface of the wafer thereby planarizing the surface of the wafer. The angle between the stream of particles and the wafer plane is preferably less than thirty degrees. The particles may be argon ions and may be chemically active particles or physical particles.
    Type: Grant
    Filed: September 17, 1990
    Date of Patent: February 25, 1992
    Assignee: National Semiconductor Corp.
    Inventor: Michael E. Thomas
  • Patent number: 5088053
    Abstract: A video signal processing system includes a memory for holding digital data, input and output channel circuitry for reading data from and writing data to the memory and processing circuits for processing data read from the memory to produce data to be written to the memory. Each of the input and output channels produces two types of memory request signals, a normal request signal and an urgent request signal. The normal request signal is produced to gain access to the data in the memory for normal read and wire operations. The urgent request signal is produced to access the memory when the processing circuitry is in a paused state waiting either to obtain data from the input channel or to provide data to the output channel. The normal read and write request signals are handled with substantially equal priority by first scheduling circuitry. The urgent request signals are handled by second scheduling circuits according to a fixed priority scheme.
    Type: Grant
    Filed: November 16, 1987
    Date of Patent: February 11, 1992
    Assignee: Intel Corporation
    Inventors: David L. Sprague, Allen H. Simon, Alfred Kwan