Abstract: A multi-processor chip has several processor cores that are simultaneously tested in parallel. The processor cores each have identical scan chains that produce identical test results absent defects. Expected test data is scanned from an external tester onto the chip and replicated to each processor core's scan chain. The expected test data is compared to scan chain outputs at each processor core. Any mismatches set a test-fail bit for that processor core. Each processor core has repairable scan chains and a separate critical scan chain. Failures in the critical scan chain in any processor core cause the whole chip to fail. Processor cores are disabled that have failures in their repairable scan chains, allowing the chip to be repairable by using the remaining processor cores. Critical scan chains include logic that drives to other blocks on the chip, while repairable scan chains have logic embedded deep within a processor core.

Abstract: A printed-circuit board (PCB) module has co-planar solder pads on a bottom surface. The solder pads can be surface-mounted to pads on a main board, allowing the PCB module to be surface mounted without wire leads extending from the PCB module substrate. A cavity is formed between the solder pads on the bottom surface. The cavity is formed by milling away some of the thickness of a sacrificial insulator layer, which is the insulator layer under the solder-pad metal layer. The sacrificial insulator layer can be made thicker to allow for milling the cavity without milling into inner metal layers on the PCB module. After milling away much of the sacrificial insulator layer, stand-offs remain under the solder pads, providing a stand-off gap between the top of the cavity and the solder pads when soldered to the main board. The stand-off gap allows for cleaning under the PCB module.

Abstract: Several cluster chips and a shared main memory are connected by interconnect buses. Each cluster chip has multiple processors using multiple level-2 local caches, two memory controllers and two snoop tag partitions. The interconnect buses connect all local caches to all snoop tag partitions on all cluster chips. Each snoop tag partition has all the system's snoop tags for a partition of the main memory space. The snoop index is a subset of the cache index, with remaining chip-select and interleave address bits selecting which of the snoop tag partitions on the multiple cluster chips stores snoop tags for that address. The number of snoop entries in a snoop set is equal to a total number of cache entries in one cache index for all local caches on all cluster chips. Cache coherency request processing is distributed among the snoop tag partitions on different cluster chips, reducing bottlenecks.

Abstract: Multi-phase clocks are used to encode and decode signals that are phase-modulated. The input signal is phase-compared with a feedback clock. Phase differences increment or decrement an up/down counter. The count value from the up/down counter is applied to a phase rotator, which selects one clock phase from a bank of multi-phase clocks. The multi-phase clocks have the same frequency, but are offset in phase from each other. An output divider divides the selected multi-phase clock to generate a phase-modulated output. A feedback divider divides a fixed-phase clock from the multi-phase clocks to generate the feedback clock. An analog or a digital front-end may be used to convert analog inputs to digital signals to increment or decrement the counter, or to encode multiple digital bits as phase assignments. For a de-modulator, a digital-to-analog converter (DAC) or a digital decoder produces the final output from the count of the up/down counter.

Abstract: A memory system provides data error detection and correction and address error detection. A Single-byte Error-Correcting/Double-byte Error-Detecting (SbEC/DbED) code with the byte being a 4-bit nibble is used to detect up to 8-bit errors and correct data errors of 4 bits or less. Rather than generating address parity, which is poor at detecting even numbers of errors, a cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to just 4 address check bits using the CRC code. The 4 address check bits are merged (XOR'ed) with two 4-bit nibbles of the data SbEC/DbED code to generate a merged ECC codeword that is stored in memory. An address error causes a 2-nibble mis-match due to the redundant merging of the 4 address check bits with 2 nibbles of data correction code. The CRC code is ideal for detecting even numbers of errors common with multiplexed-address DRAMs.

Abstract: A loop-back extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module under test. An Advanced Memory Buffer (AMB) on the memory module fully buffers DRAM chips on the memory module. The AMB inputs from and outputs to the test socket differential northbound lanes (toward a processor) and southbound lanes (away from the processor). The extender card has northbound loopback traces that connect northbound lane outputs from the memory module back to northbound-lane inputs to the memory module. Southbound loopback traces connect southbound lane outputs from the memory module back to southbound-lane inputs to the memory module. The loop-back extender card allows the AMB to perform loopback testing without modifying the PC motherboard. Series/shunt resistors can be placed on the loopback traces, or serpentine traces can be used to increase loopback delays.

Abstract: Red, Green, Blue (RGB) pixels in a Beyer pattern are converted to YUV pixels by a converter. The converter does not interpolate RGB pixels to fill in missing RGB color values but instead performs interpolation during conversion to YUV. An edge-enhancement filter is applied to the preliminary Y values to generate final Y values with sharpened edges. The final Y values are combined with R or B pixels from the Beyer pattern to generate U and V chrominance values. Since the preliminary luminance Y values are edge-enhanced, and then the edge-enhanced Y values are used to generate the U, V, values, enhancement improves U and V values as well. Rather than use full-frame intermediate buffers, a 7-line RGB buffer, a 5-line preliminary Y value buffer, and a 3-line final Y buffer can be used.

Abstract: Hot air blown past memory modules under test in a heat chamber is improved. Hot air entering the chamber from an inlet pipe is split by a manifold and deflectors. Holes in the manifold allow for a relatively even air distribution within the chamber, minimizing temperature variations. Return air is collected by a heat-chamber bottom cover into a return pipe. A heating unit re-heats the return air and blows it into the inlet pipe. One side of the heat chamber is an insulated backplane. Memory modules are inserted into sockets on module motherboards, which are inserted into motherboard sockets on the backplane. On the other side of the backplane, card sockets receive pattern-generator cards outside the heat chamber but electrically connected to the module motherboards through the backplane. The pattern-generator cards exercise the memory modules. The pattern-generator cards are cooled while memory modules in the heat chamber are heated.

Abstract: A multi-light-emitting diode (LED) display for a USB flash drive produces a visually dazzling display. When accessed, a USB flash controller drives pulses onto an activity signal that increments a counter on a pattern-decoding generator. The pattern-decoding generator decodes the count and drives signals to data outputs. The data outputs connect to LED's, turning LED's on and off according to a display pattern. The pattern can be programmed by the USB flash controller into the pattern-decoding generator, or can be a hardwired pattern. Marquee patterns having a lit LED appearing to move down a line of LED's have more visual appeal than single LED indicators. Each data line can drive two LED's in different parts of a dual display, reducing costs. Multi-color LED's can be used to improve variety. The multiple LED's and the pattern-decoding generator can be mounted on a flexible PCB.

Abstract: Electronic devices packaged with arrayed solder balls, leads, or pads, such as Ball Grid Array (BGA) devices, are stacked together. Each stack has a bottom adapter card with metal contacts on a top surface in an array to match the array of solder balls of a lower BGA package, and final bonding pads on a bottom surface that are soldered to an underlying motherboard or printed-circuit board (PCB). An upper BGA package has its solder balls connected to a matching array of metal contacts on a top surface of an intermediate adapter card. Metal traces on the intermediate adapter card connect to lead frame pins that wrap around the edge of the intermediate adapter card and make contact with peripheral pads on the top surface of the bottom adapter card. Lead frame pins and peripheral pads can connect several intermediate adapter cards together with one bottom adapter card.