Abstract: A memory device having a programmable device width includes a storage unit, output logic, at least one register, control logic, decode logic and configuration logic. The output logic outputs data from the storage unit based on control signals and address data received on address inputs. The register stores device width data under the control of the control logic. The control logic receives command data, and generates the control signals based on the command data. Additionally, the control logic controls the storage operation of the register based on the command data. The decode logic decodes the device width data to determine a desired device width, and the configuration logic configures the output logic so that the memory device has the desired device width.