Abstract: An integrated circuit package having a top opening and a cavity, with a chip adhered in the cavity. The top opening has routing strips electrically connecting the top opening with the outer surface. The routing strips are electronically connected to bonding pads located in a central area of the chip. Following assembly of the components, the top opening and the cavity are encapsulated in a molding process. A method is provided for forming a substantially flat integrated circuit package.

Abstract: A thin, stacked face-to-face integrated circuit packaging structure includes a chips attached to both major surfaces of a rigid interposer, and interconnected by printed wiring traces and vias to external solder ball contacts attached to the interposer.

Abstract: A multifunctional shipping container for integrated circuits, and methods of using and reusing the container are described. The compact container coupled with foam inserts is dimensioned to securely ship and store integrated circuits in either tray or reel format. The container with an expandable cavity allows ease of access for loading and unloading the contents at multiple work stations, and may be converted to an in-house "tote". Multifunctionality of the container supports use as a shipping system from the tray or reel supplier, to the IC assembly and test site, to distribution centers, and to the IC customer, thus eliminating multiple costs of disposal, inventory and new shipping materials.

Abstract: A semiconductor package includes a stiffener strip (10) having a die pad (18) and a body portion (12). A first surface (4) of the die pad (18) is offset from a second surface (3) of the body portion (12) a predetermined amount. The stiffener strip (10) includes an internal edge (27) concentrically disposed about the die pad (18) and tie straps (16) connecting the internal edge (27) to the die pad (18). A die (28) is affixed to the first surface (4) of the die pad (18). A substrate (20) has a first surface (17) and a second surface (19), with the second surface (19) being affixed to the first surface (2) of the body portion (12). The substrate (20) includes a window (22) and conductive elements (24). A plastic molding material (33) encompasses the die (28), at least a portion of the stiffener strip (10), and at least a portion of the substrate (20).

Abstract: A novel technique for measuring the temperature of an electronic circuit undergoing assembly packaging processes includes a non-contact infrared detector which is used to measure the temperature of the die allowing a control systems to directly adjust the die temperature. Previous to this invention, the die temperatures were controlled indirectly, typically by controlling ambient temperature in an oven or furnace to a series of set point values during curing of the electronic packaging materials.

Abstract: A method for attaching particles (12) to a substrate (14), comprising the steps of transferring adhesive areas (30) from an adhesive stamp (35) to contact pads (42) of the substrate (14), and depositing the particles (12) onto the adhesive areas (30) on the contact pads (42), thereby attaching the particles (12) to the substrate (14). The adhesive stamp (35) may comprise a stamp (20) having at least one projection (22) and an adhesive material applied thereon. The stamp (20) may be composed of silicon, silicone rubber or metal. The adhesive material may be composed of an adhesive polymer or an adhesive flux.

Abstract: The invention relates to a single piece leadframe that can be used in current semiconductor device production. The leadframe has a plurality of segments in a horizontal plane, a chip mount pad in a different horizontal plane, and another plurality of segments connecting said chip mount pad with said leadframe. The latter plurality of segments has a geometry designed so as to tolerate bending and stretching beyond the limit of simple elongation based upon the inherent material characteristics. The chip mount pad of said leadframe provides direct thermal contact to an external heat conductor or heat sink by being designed so as to extend through the encapsulating package. The exposed chip pad can also be used electrically as a ground connection.

Abstract: A method for populating an substrate (14) with particles (12, 16), comprising the steps of applying an adhesive coating (22) to both surfaces of a substrate (14) and loading the particles (12, 16) to the adhesive areas (30) of the adhesive coating (22), such that each surface of the substrate (14) is fully populated with the particles (12, 16) which may thereafter be reflowed simultaneously. The particles may be composed of a variety of compositions, including copper, other metals, alloys, and synthetic resin compounds, such as conductive plastics.

Abstract: A polymeric three-layer membrane having metal-filled microscopic pores extending through the complete thickness of the membrane, including a central restraining core layer, and an adhesive layer on each surface of the core layer. The membrane is used to form interconnects between electronic parts.

Abstract: A three-dimensional microchip circuit assembly process, wherein a three-layer dry adhesive film sandwich is used to prepare a stacked circuit cube.

Abstract: A hermetic packaging technology for silicon Schottky die or any other two terminal solderable die. The technology uses a pressed ceramic frame, solid metal pads, a solid metal disc, metal seal rings, and a direct high temperature solder bond to the die. There are no intermediate straps or wires used to connect the die to the metal pads. The die is actually part of the final package, or it can be said that the package is built around the die. The device is hermetically sealed for use in high reliability applications such as military or space programs. All materials used in the technology are matched for coefficient of thermal expansion (CTE).

Abstract: The present invention is directed to a semiconductor device and method wherein a vertical opening is provided or formed completely through a semiconductor substrate of the semiconductor device to print an external electrical contact to be made to one of the semiconductor regions of the semiconductor substrate. In the disclosed embodiment an electrical contact is also provided to the bottom portion of the semiconductor substrate.

Abstract: The invention discloses a method for forming solder (114) on a substrate (112). The method includes forming a decal (110) with a plurality of solder regions (113). The method further comprises aligning the decal (110) with the substrate (112) and transferring the solder regions (113) on the decal (110) to the substrate (112).

Abstract: A three-dimensional semiconductor circuit assembly wherein each of several circuit chips is provided with patterned metal layers that extend from the circuit surface onto an edge side of the chip, then the chips are adhesively bonded to opposite surfaces of one or more dielectric spacers, respectively, whereby the edge sides of the resulting multiple-chip stack are readily connected to metal patterns on a substrate.

Abstract: A surface mount package for use with large area silicon device. The package uses a pressed ceramic frame and solid metal pads which are closely matched for coefficient of thermal expansion (CTE) to each other and to the silicon die. The package is specifically designed for large area die (greater than 0.0625 inches squared) and for high temperature eutectic alloy bonding. All materials of the package are CTE matched to each other and to silicon within 10%.

Abstract: First and second electronic devices interconnected by a nonconductive nanoporous film, the film having metal-filled pores extending through the thickness of the film, such that each of the devices is contacted by the metal in at least several pores, the film having other pores that remain unfilled, in order to enhance the compressibility of the film.

Abstract: First and second electronic devices interconnected by a nonconductive nanoporous film, said film having metal-filled pores extending through the thickness of the film, such that each of said devices is contacted by the metal in at least several pores, wherein said film comprises a silicone polymer.

Abstract: First and second electronic parts interconnected by a nonconductive nanoporous film having first and second parallel surfaces, said film having metal-filled pores extending through the thickness of the film, such that each of said parts is contacted by the metal in at least several pores, a number of the pores being perpendicular to the surfaces of the film, and other pores being oblique to the surfaces of the film, whereby thermal dissipation is enhanced in the plane of the film.

Abstract: First and second electronic parts interconnected by a nonconductive nanoporous film, said film having metal-filled pores extending through the thickness of the film, such that each of said devices is contacted by the metal in at least several pores, wherein said film comprises liquid crystal or rigid rod polymer films.

Abstract: A low-capacitance antifuse (34 or 76) is provided for use in user-programmable integrated circuitry. The antifuse includes first (38 or 80) connection metal layers and second (54 or 94) connection metal layers. Between the metal layers is dielectric layer (52 or 82), and between the dielectric layer and at least one of the metal layers is a conductive layer in the form of pillar (40) or stack (81). The pillar or stack extends the separation between the metal layers thereby decreasing the capacitance of the antifuse.