Abstract: Arbitration circuit operates for common bus access granting where the asynchronous access requests are latched in a register by the rising edge of a periodical square wave timing signal, and from there transferred to a logical priority network, implemented with a programmable logic array.

Abstract: Memory control circuitry is disclosed for providing memory refresh during battery back-up operation. Memory addressing circuitry is connected between circuitry, such as a processor, providing memory refresh addresses, and memory addressing inputs. During normal main power supply operation, refresh addresses are provided to the memory from the processor. Upon occurrence of a main power supply failure, and start of battery back-up operation, the last refresh address provided by the processor is stored in the memory addressing circuitry and successively incremented to provide refresh addresses to the memory .

Abstract: A Floating Point Processor or Floating Point Unit (FPU) with capability for performing exponent/sign-related calculations concurrently with mantissa-related calculations. The operation of the FPU within the context of a general purpose digital computer system is shown. The FPU has control, mantissa, and exponent/sign functional blocks which have unique architectural arrangements and interconnections therebetween, and also have interfacing structure for connecting system control and clock signals to the control block. The operation of the FPU is timed in a particular manner to permit its operation to be transparent to, or to not impact operation of the CPU, when the FPU communicates with main memory or the CPU.