Abstract: Needle printing head of the permanent magnet type where the armatures of a plurality of printing actuators are attracted, in rest position, against the poles of a permanent magnet and released in printing position by the "cancellation" of the magnetic flux caused by control windings and where the impact of the armatures against the permanent magnet poles, when they return to the rest position is damped by a multilayer element interposed between armatures and magnetic poles and consisting in two thin sheets of magnetic steel between which a thin film of resilient material such as polyester is interposed.

Abstract: Belt tensioning apparatus for a serial printer wherein a spring imparts a predetermined pull to driving belt by applying a predetermined force to a slide on which a belt return idle pulley is mounted, and wherein a slide is offset from a working point and in the direction opposite to the force exerted by the spring by an amount controlled by a stop pad, preferably resilient and position adjustable, or automatically changeable in position owing to belt elongations occurring during operation.

Abstract: Any host requesting acccess to the bus must, on its first attempt, wait for N arbitration delay periods after the bus becomes available before attempting to take control of the bus. If another host takes the bus before completion of the arbitration delay period, the host must wait till the next time the bus becomes available. The arbitration delay count is decreased by one for each successive attempt, until the host either gains control of the bus or the aribration delay period goes to zero. At this point it may attempt to take control of the bus as soon as the bus becomes available. If another higher priority host reaches an arbitration delay count of zero during the same arbitration delay count period, the host will be denied and will wait for the next time the bus becomes available, again with an arbitration delay count of zero.

Abstract: In accordance with the present invention, there is provided a system for logging an error that occurred in a multi-chip memory storage device in a data processing system. The system has a mechanism for detecting an error and for receiving data and check bits associated therewith. The mechanism for detecting an error generates syndrome bits as a function of the data and of the check bits. Connected to the error detecting mechanism is an error logging mechanism which is adapted to receive the syndrome bits and to determine the chip in which the error occurred.

Abstract: A system and method for detecting an error that occurred in a multi-chip memory storage device in a data processing system. The system detects an error and receives data and check bits associated therewith. A process that uses the principle of scrubbing and incorporates high speed error flags distinguishes between hard and soft errors.

Abstract: A memory address controller addresses two memories and selectively modifies an address before it is applied to the addressing input of one of the two memories. A bit of the address is used to indicate to the controller if the address is to be modified. The same address is applied unchanged to the addressing input of the other of the two memories by the memory address controller. In this manner the addressing range is expanded.

Abstract: A data selection matrix is disclosed which uses a plurality of programmed array logic (PAL) units having input thereto portions of binary words from a plurality of sources, the PALs being responsive to control words also input thereto to jointly select one of said sources of binary words and to select the arrangement of the portions of the binary words being input thereto from the selected source of binary words.

Abstract: A firmware controlled microprocessor plugged into a printed circuit board received firmware signals from a control store mounted on the printed circuit board. The number of pins required for transferring firmware signals is reduced by time sharing pins with firmware signal required for the full cycle of operation and firmware signal required only during the second half of the cycle of operation.

Abstract: In a computer terminal an electronic device allows the selection of the terminal address and baud rate via a DIP switch (Dual In-Line Package) located internally in the terminal or via external selection means by allowing the setting of signal line voltage level by means of jumper wires in a communication connector. To enable the external option, predetermined pins in the communications connector are jumpered to disable the DIP switch, whose settings are then ignored. By jumpering other predetermined pins in the communications connector, the signal line levels define the terminal address and the terminal baud rate.

Abstract: A memory bank selection arrangement has a memory which is made up of smaller memories each of which has a number of banks of memory. First bits of a memory address are used by an address controller for addressing a location in a selected bank of a first of the smaller memories. The address may be incremented by the controller before being used to address a second of the smaller memories, and a carry output is generated when the first bits are incremented and there is a carry from the highest order bit thereof. The memory address also includes second bits which are input to an adder which increments the number represented by the second bits responsive to the carry out from the controller to compensate for the incrementation of said first bits. The incremented or unincremented number output from the adder is used by a selector to select a bank of the smaller memories so that they can be addressed using the incremented or unincremented first bits.

Abstract: A data processing system includes a number of subsystems all coupled in common to a system bus and communicate with each other by sending and receiving commands sent over the system bus. A central processing subsystem includes a response memory for storing indication of the responses sent by the receiving subsystem when receiving commands sent by the central processing subsystem. The responses include an acknowledge response, a not acknowledge response or no response--a timeout. Storing the acknowledge response and the timeout will enable the programmer to determine which of the three responses was received.

Abstract: In a multi-tasking data processing system, each task may request that the operating system set up descriptor blocks which identify virtual screens for display of data on the video display. Under keyboard control, only one virtual screen is selected for display at a given time. The operating system reserves a portion of the video display for displaying identifiers of the virtual screens which have been established but which are held in background. Each virtual screen may be subdivided into viewports by the corresponding application task. Those viewports are also identified in the operating system by descriptor blocks which point to pages of data in the document files. The descriptor blocks can be modified through requests from application tasks even when held in background. Whenever the display memory is updated, data designated by the descriptor blocks is passed through a rasterizer in the operating system which generates the pixel data to be stored in a display memory.

Abstract: A generalized method and apparatus for compression and decompression of textual information. Compression is performed by reading in succession each character and an associated context of a text, selecting for each character and associated context a corresponding code character, and providing the resulting code characters as the compressed form of the text. Decompression is a symmetric, inverse operation wherein the contexts associated with the code characters are read from a known decompressed portion of text. The context of a character is a group of text characters associated with a text character and containing a fixed number of characters. Text and code characters and contexts are related through a table containing a relative alphabet for the contexts of the language of the text.

Abstract: A task control method and apparatus for controlling the interactive, concurrent execution of a plurality of general purpose data processing tasks in a data processing system. The system includes a memory for storing active tasks, a mass storage means for storing inactive tasks and a general purpose CPU. Upon request by a user or by an active task, a task loader transfers a presently inactive task from the mass storage means to the memory to be available for execution. A memory manager assigns a task node space in the memory and a task manager creates a task control block for the task to be activated, assigns a task control block identification to the task control block, and writes the task control block identification into the task's task node space to link the task to the task's task control block.

Abstract: A document processing system including a control structure having separated supervisory and document functions. The document functions, including a document buffer and document access control means are the sole means for accessing documents and the document function routines are selected from predetermined library of such routines. The system includes a flexible, expandable document structure incorporating information item blocks and indexing blocks related through pointers and means for applying visual and informational attributes to document text.

Abstract: A power switching means for connecting a power source to a digital data processing system. The switching means includes a power switch for connecting the power source to the system and two control switches. A first control switch determines whether system power is to be turned on or off and is responsive to a turn-on selection signal to provide an initial turn-on signal to the power switch if a power turn-on is to be performed. The second control switch is responsive to a power turn-on/turn-off initialization signal to initiate and control the turn-on and turn-off operations. The second control switch is responsive to the initialization signals at power turn-on to enable the first control switch to be responsive to a power-on selection signal to provide the initial turn-on signal to the power switch.

Abstract: A non-blocking exchange switch for communicating information samples between points, including a time slot interchange, a voice conferencing system and a network interchange. The time slot interchange includes an interchange memory having a single storage location associated with each point connected from the switch. A point address memory provides point addresses corresponding to points and associated interchange storage locations. A connection memory provides corresponding connection addresses corresponding to interchange storage locations associated with points with which a point is communicating. The voice conferencing system includes a conference memory means providing conference addresses corresponding to points in a conference connection, and a sample memory means for storing individual samples from corresponding points. A conference processor means provides corresponding conference samples to conference communicating points, each conference sample comprising a summation of individual samples.

Abstract: A data processing machine in which the cache operating cycle is divided into two subcycles dedicated to mutually exclusive operations. The first subcycle is dedicated to receiving a central processor memory read request, with its address. The second subcycle is dedicated to every other kind of cache operation, in particular either (a) receiving an address from a peripheral processor for checking the cache contents after a peripheral processor write to main memory, or (b) writing anything to the cache, including an invalid bit after a cache check match condition, or data after either a cache miss or a central processor write to main memory. The central processor can continue uninteruptedly to read the cache on successive central processor microinstruction cycles, regardless of the fact that the cache contents are being "simultaneously" checked, invalidated or updated after central processor writes.

Abstract: Microinstruction selection circuitry effects the selection of successive microinstructions of a sequence. Current and next PCs are stored in first and second registers. Current PC is provided to a memory from one register to fetch a current instruction from memory while a next PC is generated and stored in the other register. At end of a current instruction, next PC becomes current PC and a new next PC is generated and stored in the register previously storing the former current PC.