Abstract: A composite dieletric film for final passivation of an integrated circuit. First, plasma-enhanced TEOS oxide is deposited to a thickness of 2000 .ANG., followed by thermal O.sub.3 -TEOS oxide to a thickness of 8000 .ANG., and then silicon nitride to a thickness of 10,000 .ANG..

Abstract: photosensor device (41) having tapered photodiodes (53, 55) that are interdigitated and which is compatible with typical ASIC, CMOS and BiCMOS processes. A left side photodiode array of tapered regions (53) of a first conductivity type is disposed into an epitaxial layer of a second conductivity type. This array of photodiodes is coupled together and further coupled to a first output terminal (43). A fight side photodiode array of tapered regions (55) of said first conductivity type is disposed into the epitaxial layer of the second conductivity type, spaced apart from the left side photodiode by a minimum distance. A second output terminal is coupled to the array of fight side photodiodes (51). An incident light spot (39) is focused onto the sensor. The amount of current generated at the first and second output terminals (43, 51) will be proportional to the area of the left photodiode array and the area of the fight photodiode array which is receiving light.

Abstract: A photosensor device (41) having tapered photodiodes (53, 55) that are interdigitated and which is compatible with typical ASIC, CMOS and BiCMOS processes. A left side photodiode array of tapered regions (53) of a first conductivity type is disposed into an epitaxil layer of a second conductivity type. This array of photodiodes is coupled together and further coupled to a first output terminal (43). A right side photodiode array of tapered regions (55) of said first conductivity type is disposed into the epitaxial layer of the second conductivity type, spaced apart from the left side photodiode by a minimum distance. A second output terminal is coupled to the array of right side photodiodes (51). An incident light spot (39) is focused onto the sensor. The amount of current generated at the first and second output terminals (43, 51) will be proportional to the area of the left photodiode array and the area of the right photodiode array which is receiving light.

Abstract: A chuck (82) for lamp-heated thermal and plasma semiconductor wafer (38) processing comprises an absorbing surface (171) for absorbing optical energy from an illuminator module (84) that transforms the electrical energy into radiant optical energy. Chuck (82) includes an absorbing surface (171) that absorbs optical energy and distributes the resultant thermal energy. From the absorbing surface, a contact surface (168) conducts the heat energy to semiconductor wafer (38) and uniformly heats the semiconductor wafer (38) with the distributed thermal energy. Chuck (82) not only provides significantly improved process temperature uniformity, but also allows for the generation of RF plasma for plasma-enhanced fabrication processes as well as for in-situ chamber cleaning and etching. Additionally, chuck (82) provides at least two methods of determining semiconductor wafer temperature; a direct reading thermocouple (112) and association with the pyrometry sensor of illuminator module (84).

Abstract: A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.

Abstract: A manufacturing system has a material handling system that uses free roaming mobile apparatuses that are under the control of a visual navigation system that has the capability of regenerating images that are temporarily obstructed from view of a visual navigation system. The visual navigation system uses the images to provide commands that navigate an electrical controllable apparatus such as a mobile robot. The mobile robot is fitted with a minimum of three navigation beacons which emit a light visible to overhead television cameras. The beacon area is arranged so as to form a triangle. The shape and dimension of the triangular pattern is measured and stored in a memory unit within the visual navigation system. When a beacon is blocked from view of the television cameras, the visual navigation will regenerate coordinate of the blocked beacon and provide the necessary navigation commands to the mobile apparatus.

Abstract: A semiconductor integrated circuit device including a signal line connected at one point thereof to a source of a signal voltage variable between high and low levels and a source of an activating signal variable between high and low voltage levels, wherein at least one signal amplifier circuit is operatively connected to the signal line. The signal amplifier circuit is responsive to the activating signal for allowing the signal line to connect to the source of the activating signal in response to the high level of the signal voltage on the signal line in the presence of the activating signal of the high voltage level and maintaining the signal line disconnected from the source of the activating signal in response to the signal voltage of the low level on the signal line.

Abstract: This system includes a composite memory (5) in which are memorized the data for images to be displayed for each frame. A video display processor (12) controls the screen (8). A central processing unit (1) effects the composition of the image with the memory and an address processor (10), the extraction of the point data to be displayed being effected by a time base circuit (BT) synchronized with the sweeping of the screen, and by a control device (15) for dynamic access which distributes the access times among different units utilizing the memory. The memory (5) includes a first control memory for the memorization of a data word for a line or group of lines making up the image, each word having an address value for addressing a second control memory which contains, at each of these addresses, at least one display attribute data word characterizing the contents of the line(s) corresponding to the value of the respective address of the first control memory.

Abstract: An electrically programmable logic array (10) for binary signals having signal inputs A.sub.0 -A.sub.x) and signal outputs Q.sub.0 -Q.sub.i) comprises two row lines (a.sub.0,a.sub.0' -a.sub.x, a.sub.x') for each signal input. The signal applied to the signal input is generatable at the one row line in non-negated form and at the other row line in negated form. For each signal output a column line (q.sub.0 -q.sub.i) is provided.In the non-programmable state between each row line and each column line there is an electrically conductive connection interruptable for the purpose of programming. Inserted into the connection between the signal inputs and each associated row line is a controllable switching member (S.sub.0,S.sub.0',-S.sub.x, S.sub.x') which is controllable by a control signal applied thereto in such a manner that its output signal changes with the signal applied to the associated signal input or irrespective of said signal always retains a predetermined signal value.

Abstract: A CMOS random access memory has storage elements (1, 2 and 3) which produce complementary outputs on a pair of output conductors (7, 8). In order to speed up the establishment of the output voltages on the conductors two cross-connected transistors (22, 23) are provided to supplement the discharging of that conductor which is to have the lower voltage, each transistor being responsive to the voltage on one conductor to discharge the other conductor. The correct timing of the operation of the cross-connected transistors is provided by two further transistors (26, 27) having their gates respectively connected to the conductors which are arranged to become conducting when an adequate voltage charge has been achieved by the storage element. When either of the further transistors conducts a transistor (24) in series with the two cross-connected transistors is turned on to enable them to operate.

Abstract: An injection mold is described for producing the housings of integrated circuits. The injection mold icludes a first mold half (30) in which are disposed a number of mold recesses (46) corresponding to the number of housings to be made simultaneously, having a depth corresponding to a portion of the height of the housings, and supply passages (48, 50, 52, 54, 56, 58) leading to the mold recesses (46). In a second mold half (32) which is adapted to be brought in the closure direction into engagement with the first mold half (30) a number of mold recesses (76) equal to the number in the first mold half (30) are disposed in corresponding arrangement, the depth thereof being equal to the remaining portion of the height of the housings to be made. The mold recesses (46) in one of the mold halves (32) are disposed groupwise in mold portions (64) which are held in the one mold half (32) displaceably in the closure and opening direction.

Abstract: A protective circuit arrangement is described for protecting semiconductor components connected to input and output terminals (10) against overvoltages in bipolar integrated circuits. The circuit arrangement contains at least one supply voltage terminal (12) and a ground terminal (14). Between the ground terminal (14) and at least the input and output terminals (10) which are connected to components sensitive to overvoltage a thyristor-tetrode (22) having a first control electrode (28) and a second control electrode (30) is inserted, the first control electrode (28) being connected to a line (18) which in the operative state of the integrated circuit lies at a voltage above the ground potential and the second control electrode (30) being connected to the ground terminal 14.

Abstract: MESFET devices are fabricated on a semiconductor substrate using a LOCOS (localized oxidation of silicon) process twice during the fabrication. The first LOCOS process provides device separation with a self-aligned thick-field oxide (SATO). The second LOCOS provides separation of gate and source/drain regions for each device, and self-aligns the gate contact with the channel implant. Devices fabricated by this method exhibit reduced series resistance, and improved metal step coverage.

Abstract: Non-volatile JRAM cell having interelectrode non-volatile capacitance which is readable and varies with the electrical charge on elements of the device. To program the nonvolatile capacitance, the address lines (word line and bit line) are biased so that a charge is given to the nonvolatile multidielectric stack between the MIS gate and the JFET source of the cell. For a charge of one polarity, an inversion layer of electrons (for a P-type substrate) is formed on the surface of the JFET source, increasing the capacitance between the MIS gate electrode and the JFET gate electrode. For the opposite polarity, an accumulation layer forms at the JFET source surface, decreasing the interelectrode capacitance. The cell is read by presetting one address line, floating that line, then putting a pulse on the other line while reading the voltage output on the floating line.

Abstract: Transportation apparatus comprising two parallel chains extending in the transport direction. Workpiece carriers are disposed between the chains and extend parallel to each other. Each workpiece carrier includes two support elements extending parallel to each other and are rigidly connected together. On each workpiece carrier, a plurality of workpiece clamps are disposed. Each workpiece clamp comprises two clamp members, respectively connected to the support elements. At least one clamp member of each workpiece clamp is pivotal about the support element with which it is connected, between a closed position and an open position. The chains are fed between a charging station, at which the workpiece clamps are changed with workpieces, and a discharge station at which the workpieces are released from the clamps.

Abstract: An inverter which includes a resonant electrical circuit and a charging transistor arranged to charge an energy storage component of the resonant circuit periodically in synchronism with oscillations in the circuit so as to maintain the oscillations. A part of the oscillatory energy of the resonant circuit is transferred to an output circuit so that the inverter supplies output power.The charging transistor forms part of a current-limiting switch and is controlled by a control circuit which is arranged to monitor the voltage across the transistor and to switch it on when the voltage lies between first and second limits, one of which preferably is at or near zero, and changing in a predetermined sense, such as to charge the resonant circuit in synchronism with oscillation thereof. The charging transistor then adds energy to the resonant circuit until the current-limit is reached. Charging is then stopped by the switching off of the transistor.

Abstract: A polyfunction programmable data receiver comprising means for receiving a string of serial data followed by a control signal; means for detecting said signal comprising a pulse length analyzer, and a counter and a comparator; bidirectional means for setting up a digital word to be identified or for providing in parallel the data of said string according to the status of a mode selection circuit; means for providing an output signal if the comparison between said serial string and said set up digital word is favorable when the receiver operates as identifier, or an enabling signal when the receiver operates as a series/parallel converter. Some applications of this circuit are also disclosed.

Abstract: A semiconductor switch device suitable for a.c. power control includes three 4-layer switch components in parallel in a single body of semiconductor material. First and second components are of the same polarity and of opposite polarity to the third component. One end connection of the second component is taken out as a secondary gate connection separate from the corresponding connections of the first and third components. In a preferred mode of use, the secondary gate connection is maintained at a d.c. potential relative to the corresponding connections of the first and third components so as to enable the second component to be conducting during the zero crossings of the a.c. supply and able to maintain the internal voltages required for conduction of either or both of the other components.

Abstract: A method for the fabrication of a cured polyamic acid film having apertures therein selectively etched to provide sidewalls sloped at a controlled angle. Such films are used in the fabrication of integrated circuits having two or more levels of metallization, to provide electrical insulation between metal levels. The apertures therein are required to have sloped sidewalls in order to enhance the yields of circuits having reliable contact between metal levels.

Abstract: A matrix array of objects, for example semiconductor bars, is located on a carrier such as an X-Y table and the objects are successively brought into the field of view of a television camera for precise alignment with respect to a reference point. Video signals corresponding to an image of the object and its peripheral area are digitized to produce digitized video signals predominantly of a first level corresponding to surface areas of the object and of a second level corresponding to the peripheral areas. The digitized video signals are analyzed during a plurality of data window sets which are associated with axial directions corresponding to directions of movement of the X-Y table and which correspond to areas of the video image which are in a defined position relative to different edges of the video image of the object when the latter is in an aligned position.