Abstract: A compact, volatile organic compound removal system is presented. The system has a metal condensation plate and a cooling source in intimate thermal contact with the metal condensation plate. The metal condensation plate has a channel formed in the plate, an inlet in the condensation plate for introducing a gas carrying volatile organic compound vapors into the channel, a high surface area metallic structure, such as foamed metal or metallic fins, in intimate contact with the walls of the channel, an outlet in the condensation plate for removing the gas from the channel and a drain in the condensation plate for removing volatile organic compound condensates from the channel. The cooling source cools the channel walls and the high surface area metallic structure so that the volatile organic compound vapors condense on the high surface area metallic structure to be removed from the gas.

Abstract: A methodology of creating integrated circuits with improved noise isolation is presented. The circuitry of an integrated circuits is separated into noise generating circuit blocks and noise sensitive circuit blocks. N-type and P-type diffusion guard rings are placed around each of the circuit blocks. Substantially overlying the N-type and P-type diffusion guard rings are power supply meshes which are intimately in contract with the guard rings below through spaced apart vias. The power supply meshes not only supply power for the circuit blocks, but also reverse-bias the diffusion guard rings for improved noise isolation.

Abstract: A method of extending promotional discounts and special prices on items for sale to identified consumers. After the identification of a consumer by a unique identifier; a selected item is promoted with a discount or special price to the identified consumer. The discount or special price is granted upon a purchase of the item by the identified consumer prior to the withdrawal or termination of the promotion to the identified consumer. The withdrawal or termination of the promotion is held in abeyance upon an acknowledgment of the promotion by the identified consumer. In other words, the identified consumer must take specific action to prevent a promotional discount from being withdrawn. This inverted promotion provides for greater incentives for the consumer to provide information about his or her purchasing habits.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A process for fabricating a low-cost high-efficiency liquid cold plate is described. The process uses a metal extrusion designed with internal fluid channels that have their major cross-sectional axes aligned perpendicular to the major surfaces of the extrusion. Particular dimensions for the cross-sections of the fluid channels and their spacings permit the extrusion process to be performed simply. A simple process for fabricating fluid inlet and outlet manifolds, creating turbulent flow inside the fluid channels, a method for capping the extrusion ends, and a method for improving the surface contact with heat generating components is described.

Abstract: A method and system for distributing and redeeming electronic promotions to a consumer through the Internet or other means is provided. An account which is associated with a unique key is maintained for each consumer account. Access is permitted to the consumer account upon presentation of the unique key over the Internet. The consumer is presented discount or other promotional choices of items available in at least one store associated with the key, or a collection of such stores, over the Internet and the selections of the discount or promotional choices made by the consumer over the Internet or other means are recorded. Upon purchase of items at the associated store by the consumer, such data are received, and the selections and purchases are reconciled to record a credit in the customer account. Unlike paper or electronic coupons, no consumer action other than the selection of promotions desired is required for item purchase.

Abstract: A BiCMOS input circuit which is capable of detecting signals below a particular range, such as ECL signals, is presented. The circuit is useful in conserving the number of pins in a BiCMOS integrated circuit in that a signal below normal ECL levels can trigger special functions, such as testing. The circuit has a plurality of CMOS inverter circuits connected in series with the input node of the first inverter connected to the input terminal of the circuit and the output node of the last inverter circuit connected to the output terminal of the circuit. Diode-connected bipolar transistor created a potential difference between V.sub.CC and the source electrode of PMOS transistor of each CMOS inverter circuit in a declining fashion from the first inverter to the last inverter. The last inverter circuit has no potential difference at all so that its output has a full CMOS swing.

Abstract: A synchronous BiCMOS logic circuit which operates between two voltage supplies and has at least one input terminal, an intermediate node and an output terminal is disclosed. The logic circuit is capable of a high speed transition in response to a signal pulse from a first logic state to a second logic state at the input terminal. The logic circuit has at least one MOS input transistor of a first polarity having a gate electrode connected to the input terminal. The MOS input transistor is coupled between the first voltage supply and the output node by its source/drain electrodes. A first current supply connected to the output node to the second voltage supply and weakly holds the intermediate node low when the logic circuit is in an initial state with the MOS input transistor turned off.

Abstract: The present invention provides for a sense amplifier having a pair of input nodes connected through isolating PMOS transistors to the differential input terminals of the amplifier. Each of the input nodes is also connected to the gates of a pair of carefully matched NMOS transistors and to the drain of the other of the matched pair. In addition, each of the input nodes is connected to the gate of one of two drive NMOS transistors. The drains of the drive NMOS transistors are each connected to the gates of two output PMOS transistors, the drains of which form the output terminals of the sense amplifier. The sources of the matched NMOS transistor pair are coupled to ground by a NMOS transistor and the sources of the drive NMOS transistors are coupled to ground by another NMOS transistor. When the differential signals at the input terminals are to be sensed and latched, the sources of matched transistor pair and the sources of the drive transistors are sequentially connected to ground.

Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

Abstract: An apparatus and a method for character and graphics pattern generation in a bit mapped graphics display system is disclosed that includes a pixel data manager 14 for supplying character bit maps and graphics patterns to a visible display memory 22. A character information memory 24 is utilized for the storage of character descriptive information which includes an address table 26, macro-instructions 28, 30, and 32, and character bit maps 34, 36, and 38. Each character in a set of characters has an associated macro-instruction and character bit map. The address table contains memory addresses that point to the macro-instructions. Each macro-instruction contains executable instructions that establish the size and location of a corresponding character bit map. To supply a character to the visible display memory, the pixel data manager fetches and executes a corresponding macro-instruction. Overhead burden on the central processing unit is minimized.

Abstract: A circuit for controls external bipolar buffers for an MOS peripheral device capable of operating in master end slave modes. The circuit provides for a slave mode logic block and a master mode logic block for generating a DATA TRANSMIT ENABLE SIGNAL to permit the bipolar buffer to transmit data signals from the peripheral device to a system bus. The circuit also provides for a second slave mode logic block and a master mode logic block for generating a DATA RECEIVE ENABLE block to permit the bipolar buffer to transmit data signals from the system bus to the peripheral device. Each slave mode logic block is responsive to condiion signals, such as CHIP SELECT and READ/WRITE. Each master mode logic block is responsive to timing signals and signals generated internally within the periphel device so that the master mode DATA RECEIVE and DATA TRANSMIT signals occur only in predetermined timing cycles.

Abstract: A high speed picture element generator for use in a digital facsimile receiver for reforming picture elements from decoded facsimile transmission signals. The picture element generator receives the decoded facsimile signals in the form of run length data of sequential color units in a line of picture. An input register of the picture element generator receives the run length data of a color unit, and an output register holds the picture element data. A decoder, coupled to the input register, generates the picture element data for the output register from the run length data. The decoder is also coupled to the output register so that the generated picture data fills portions of the output register unoccupied by the picture element data of previous color units.

Abstract: A system for connecting printed circuit boards to card cages. In addition to a conventional pin-and-socket connector arrangement for making signal and main power connections, the printed circuit board has a conducting pad coupled to the power traces of the board. A clip mounted in the card cage and connected to a first power source isolated from the main power source engages the pad before the conventional connectors make contact. Thus, the board is powered up first. As the board is fully seated and the conventional power and signal connections made, the power clip slides off the pad to break contact, leaving the main power source supplying power to the board.

Abstract: A fabrication method and resulting integrated circuit structure that provide a second level of interconnect, a low resistance contact strap between underlying layers which is not sensitive to alignment and low lateral diffusion polysilicon load. The method comprises the steps of providing contact openings in an insulating layer on a wafer to any desired underlying circuit layers, depositing a silicide layer on the wafer, removing selected portions of the silicide layer, depositing a polysilicon layer on the wafer, lightly doping the polysilicon layer to a level appropriate for the resistor, and then removing portions of the polysilicon along with underlying silicide.

Abstract: A method and device for decoding two-dimensionally encoded digital facsimile signals. The method includes (a) accumulating the run lengths of color change picture elements in the reference line, (b) decoding a codeword to generate a displacement value, (c) combining the accumulated run length of a reference line color change picture element and a displacement value to obtain accumulated run lengths of coded line color change picture elements, and (d) determining the difference between accumulated run lengths of a coded line color change picture element. The difference is the decoded data.

Abstract: A method and device for two-dimensionally coding digital facsimile signals, especially for the CCITT T.4 recommended standard. A line of digitized picture elements is coded with respect to a reference line of digitized picture elements. The run lengths of color units previous to color change picture elements in the coding and reference lines are accumulated, and the positions of the color change picture elements in the coding line with respect to the positions of the color change picture elements in the reference line are determined by the differences between the accumulated run lengths of the coding and reference line color change picture element and the reference line color change picture elements. The steps are selectively repeated in predetermined sequences responsive to the value of the accumulated run length differences.

Abstract: A high speed facsimile device suitable for integration using present day VLSI technology, for encoding binarily digitized picture information into run length codes. The device receives consecutive blocks of digitized picture data. In the device a run length generator unit, which is responsive to these consecutive blocks of picture data, generates the run lengths of color units in a data block. A combining unit coupled to the run length generator unit combines the run lengths of color units in more than one data block and an encoding unit coupled to the run length generator block and the combining unit generates in a pre-determined code, such as the recommended CCITT T.4 standard, the coded run lengths of color units independent of the data blocks.

Abstract: A transistor logic gate device is provided with a transistor coupled between the output terminal and a node of the internal phase splitter subcircuit to speed up switching without requiring an increase in internal current.