Abstract: Briefly, in accordance with one embodiment of the invention, an electromagnetic interference (EMI) reduction device may include a circuit and at least one heatsink. The circuit may include analog devices coupled to reduce EMI signals received by the heatsink. The devices may be specifically adapted to substantially invert or phase-shift by 180° the EMI signals received by the heatsink.

Abstract: The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.

Abstract: The present invention discloses a mask including: a first region near a corner of a feature, the first region including a first element, the first element being transparent to a light, the first element having a side that is smaller than a wavelength of said light; a second region near the corner of the feature, the second region including a second element, the second element being transparent to the light, the second element having a side that is smaller than the wavelength of the light; and a third region near the corner of the feature, the third region including a third element, the third element being opaque to the light, the third element having a side that is smaller than the wavelength of the light.

Abstract: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.

Abstract: The present invention discloses a method including: providing a substrate; and sequentially stacking layers of two or more diamond-like carbon (DLC) films over the substrate to form a composite dielectric film, the composite dielectric film having a k value of about 1.5 or lower, the composite dielectric film having a Young's modulus of elasticity of about 25 GigaPascals or higher.

Abstract: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.

Abstract: The present invention describes a method including: determining field-clustering scheme; selecting initial sample plan; establishing initial model of overlay, the initial model of overlay comprising components; and establishing efficient model of overlay from the initial model of overlay including: constructing matrices; identifying redundant components and eliminating the redundant components; and identifying highly-correlated components and determining whether to eliminate the highly-correlated components.

Abstract: A method for forming a high mechanical strength, low k, interlayer dielectric material with aluminosilicate precursors so that aluminum is facilely incorporated into the silicon matrix of the material, and an integrated circuit device comprising one or more high-strength, low-k interlayer dielectric layers so formed.

Abstract: A reflective mask may include an anti-reflective (AR) coating on an absorber layer to improve inspection contrast in an inspection system using deep ultraviolet (DUV) light. A silicon nitride (Si3N4) AR coating may be used on a chromium (Cr) or tantalum nitride (TaN) absorber layer.

Abstract: The present invention discloses a method of confining a liquid metal alloy within a closed-loop system; distributing a first portion of the liquid metal alloy in a cavity within the closed-loop system; turning on an electromagnet to generate a magnetic field to permeate flexible sidewalls of the cavity; attracting the liquid metal alloy in the cavity towards the electromagnet to expand the flexible sidewalls; inducing a second portion of the liquid metal alloy to enter the cavity from an inlet end of a pipe within the closed-loop system; turning off the electromagnet; repelling the liquid metal alloy in the cavity away from the electromagnet to contract the flexible sidewalls; and inducing a third portion of the liquid metal alloy to exit the cavity to an outlet end of the pipe.

Abstract: The present invention discloses an apparatus having a platen; a polishing pad disposed over the platen; a slurry dispenser disposed over the polishing pad; a cathode connected electrically to the polishing pad; a wafer carrier disposed over the polishing pad; an anode connected electrically to the wafer carrier; and a power supply connected to the anode and the cathode. The present invention further discloses a method to remove a surface layer from a wafer using a polishing pad, a slurry, and an electrical current.

Abstract: The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer. The present invention further includes a structure having a substrate, the substrate having a device; an insulator disposed over the substrate, the insulator having an opening, the opening disposed over the device; a barrier layer disposed over the opening; a seed layer disposed over the barrier layer; and a protection layer disposed over the seed layer.

Abstract: According to one embodiment a broad-angle multilayer (ML) mirror system is disclosed. The ML mirror includes a multiple layer structure configured to provide uniform reflectivity over a wide range of angles with small phase shifts.

Abstract: The present invention describes an aperture including: an opaque plate; two sliver openings located in the opaque plate, the two sliver openings having rectangular shapes, the two sliver openings being parallel to each other. The present invention further describes a method including: decomposing a pattern into horizontal sub-features and vertical sub-features; forming a first mask corresponding to the horizontal sub-features; forming a second mask corresponding to the vertical sub-features; forming a first aperture with two parallel horizontal sliver openings corresponding to the first mask; forming a second aperture with two parallel vertical sliver openings corresponding to the second mask; exposing a wafer using the first aperture and the first mask; exposing the wafer using the second aperture and the second mask; and exposing the wafer with the third mask.

Abstract: The present invention describes a test structure with a first set of features which is a subset of product features; and a second set of features adjacent to the first set of features, the second set occupying a smaller area than the first set and the second set being similar to the first set yet being distinguishable from surrounding structures.

Abstract: The present invention discloses a method of designing a set of two tiled masks, as well as, a mask including: a first tile, the first tile being transparent to a light, the first tile having a first characteristic linear dimension that is 15% or less of a wavelength of the light; a second tile, the second tile being transparent to the light, the second tile having a second characteristic linear dimension that is 15% or less of the wavelength of the light; and a third tile, the third tile being opaque to the light, the third tile having a third characteristic linear dimension that is 15% or less of the wavelength of the light.

Abstract: The present invention discloses a method including: providing a substrate; forming a buried oxide layer over the substrate; forming a thin silicon body layer over the buried oxide layer, the thin silicon body layer having a thickness of 3-40 nanometers; forming a pad oxide layer over the thin silicon body layer; forming a silicon nitride layer over the pad oxide layer; forming a photoresist over the silicon nitride layer; forming an opening in the photoresist; removing the silicon nitride layer in the opening; partially or completely removing the pad oxide layer in the opening; removing the photoresist over the silicon nitride layer; forming a field oxide layer from the thin silicon body layer in the opening; removing the silicon nitride layer over the pad oxide layer; and removing the pad oxide layer over the thin silicon body layer.

Abstract: A system and method for collecting radiation, which may be used in a lithography illumination system. The system comprises a first surface shaped to reflect radiation in a first hemisphere of a source to illuminate in a second hemisphere of the source; and a second surface shaped to reflect radiation in the second hemisphere of the source to an output plane.

Abstract: Embodiments are generally directed to a method and apparatus for determining compatibility between devices. In one embodiment, a table including a module's parameters and rules associated therewith is obtained from a module. The rules are applied to a slot's parameters to determine the module's compatibility with the slot upon coupling to the slot.

Abstract: Alloy memory structures and methods are disclosed wherein a layer or volume of alloy material changes conductivity subsequent to introduction of a electron beam current-induced change in phase of the alloy, the conductivity change being detected using current detection means such as photon-emitting P-N junctions, and being associated with a change in data bit memory state.