Abstract: An information handling system which efficiently processes auxiliary functions such as graphics processing includes one or more processors, a high speed processor bus connecting the one or more processors, a memory controller for controlling memory and for controlling the auxiliary function processing, a memory system, and an I/O bus having one or more I/O controllers with I/O devices connected thereto.

Abstract: A rendering method is provided that can materialize rendering processing from volume data at high speed using a surface rendering processor without restrictions on the structure of volume data to be processed. In the method, the sampling points of volume data V over a 3-D region are, in principle, arranged on the surfaces Q.sub.1, Q.sub.2, . . . Q.sub.n in equal intervals along a viewing ray L around viewing point p, and these surfaces are extracted as a set of triangles T.sub.i. Then, the volume data at each vertex of these triangles and the gradient vectors of this data are obtained by interpolation and generated as a triangle data group. High-speed volume rendering is materialized by displaying the data groups of these partially transparent triangles using a surface rendering processor. Since existing programs can be used for generation and processing of triangle data groups, there are no restrictions on the structure of the volume data to be handled.

Abstract: The present invention is a system and method of parsing system trace information to generate separate timelines of schedulable processes. System operation trace files are accurately parsed into schedulable processes without reliance on explicit context switching information provided by an operating system or trace tool. The invention accurately detects and parses nested event-pairs for display by a visualization tool, and allows a user to view either a nested or unnested visualization.

Abstract: The present invention is directed to a system and method for monitoring system performance by using a multi-phase approach. The first phase, referred to as the burst counting phase, utilizes a set of counters to identify calls and returns which are heavily used. In the second phase, referred to as the instrumentation phase, the performance characteristics of the "hot spots" are monitored through the use of hardware counters. In a symmetrical multi-processor embodiment, the performance profiler is active on all processors at the same time. Frequently executed code paths are identified in a manner that is minimally-intrusive to the system as a whole, and uses relatively little storage. The user may specify a threshold count, after which hardware monitoring begins, and the user may specify the type of hardware performance data collected. After both phases of the performance monitor are run, the data can be presented to the user in a variety of ways.

Abstract: The present invention is directed to a system and method for monitoring system performance by sampling instructions in a burst mode, rather than once per interrupt. A burst mode may be configurable for a number of instructions per burst. Furthermore, these instructions are counted using a dynamic tree structure, rather than a log, which results in substantial savings in storage. The present invention requires minimal changes to the operating system, and no changes to application code that is being monitored. No recompilation is necessary to use the present invention. In addition, the present invention provides a system and method for monitoring code segments that are disabled for interrupts, and thus are difficult, if not impossible, to monitor using prior art performance tools. In a multi-processor system, the burst mode is active on all processors at the same time, and each processor has its own dynamic tree structure.

Abstract: A data processing system includes a central processing complex consisting of one or more processor units, each of the processor units having one or more input/output channels, a transmission medium connected to each of the input/output channels, and one or more peripheral device controllers such as for controlling one or more direct access storage devices (DASD). In systems having more than one input/output channels, it is common to include a switching mechanism connected between the input/output channels and the control devices for enabling connection between one of a number of controllers and one of a number of channels. Each control device will include an automatic frame transmission function which includes apparatus and method for controlling transmission of frames of information between the control device and the channel. A queue of reconnection requests is constructed and a state machine controls the queue.

Abstract: A prior art naming module supports binding of an object to a name in a Naming Context (i.e., a directory). The present invention extends this original module to support properties (data about bindings), searching (finding bindings given constraints on properties) and indexing (for speeding up the search on certain property names). The ExtendedNamingContext (ENC) is a subclass of the OMG NamingContext (NC) that introduces properties, searching and indexing.

Abstract: The system and method of the present invention allows synchronization of processor clocks in a multiprocessor information handling system. The present invention calculates an average processor clock value for each processor being synchronized. All processors being synchronized read their clocks a predetermined number of times. The clock reading is done simultaneously by all the processors being synchronized. Each processor then calculates an average processor clock value, which is equivalent, for synchronization purposes, to the average processor clock values of the other processors. When more than two processors are being synchronized, a processor may be chosen as the primary processor. The other, secondary processors are synchronized one at a time with the primary processor. An adjustment is then made to the average processor clock values obtained, so that all average processor clock values are based on the same average processor clock value of the primary processor.

Abstract: An information handling system includes one or more work stations, each work station including one or more processing units, a memory system, and one or more I/O controllers all connected to a system bus, the I/O controllers controlling various input/output devices such as a keyboard, a mouse, a display device, communications adapters and the like, an operating system control means employing object oriented technology, and means for providing a persistent, distributed object name service. An object class is modeled as a set of relationships. One or more files are constructed which exist in the file system, each of the files capturing the semantics of the naming context objects.

Abstract: A system, method and article of manufacture for automatically inserting concurrency object services into binary classes in an information handling system employing object oriented technology, includes the steps of recognizing a constraint indicating that an object does not support concurrency and generating a concurrent version of the object. One alternative for generating a version of an object supporting concurrency is automatic transactional locking. The approach includes the steps of inheriting from the Lockable class which adds state to a class to allow object-level locking, inheriting from the Serialised metaclass which adds before and after methods to all methods of the non-concurrent version, and the object must be a RecoverableObject. Another alternative for generating a version of an object supporting concurrency is automatic per method locking.

Abstract: A method for building an objectbase of persistent objects, includes naming an objectbase collection of objects, naming each object relative to a first collection of objects using a first key, assigning, to each new object to be added to the objectbase collection, a second key, generating a third key from the first and second keys, storing each object with the associated keys generating a reference to each object in the objectbase collection from the third key and one or more system identifiers, creating an instance of an object collection in a database client, identifying a class of each object in the object collection to the instance collection, generating a stream class for persistence of element objects, identifying to the instance collection a mapping between its attributes that are persistent and the corresponding database fields, identifying to the instance collection access control information in the form of one or more predicates, and activating the element objects using the stream.

Abstract: A multimedia information distribution system includes one or more servers, each server having access to a database storing multimedia information for distribution to subscribers, each of the servers connected to a network such as an Asynchronous transfer Mode (ATM) packet switching network, a number of switching points connected to the network, each switching point accepting digital information from the ATM network and under the control of a resource manager providing one or more multimedia information streams through a coaxial switching network to one or more modems, wherein each modem is connected to a user's terminal by existing transmission media such as telephone twisted pair wires using Asynchronous Digital Subscriber Line (ADSL). In an alternate embodiment, the digital switching may be distributed using a hybrid fiber coaxial (HFC) cable technique to extend effective range of transmission.

Abstract: A multiplier efficiently multiplies signed or unsigned binary polynomial operands. The multiplier includes storage means for temporary storage of a current multiplier and a current multiplicand each of which being binary polynomials, one or more Booth decoders for examining multiplier bits iteratively in predetermined groups and presenting a Booth decoder output as one set of inputs to a plurality of delta generators and a partial product delta generator. Another set of inputs to the delta generators and the partial product delta generator is a predetermined group of bits from a multiplicand. The outputs of the partial product delta generator are multiplexed with outputs of the partial product register to provide inputs of an adder array. The adder array has outputs to a parallel adder which generates partial products which are then fed back to the multiplexor.

Abstract: A method and apparatus for detecting the null byte at the end of a character string. The method and apparatus first logically concatenates two 32-bit input values into a single 64 bit value. Next, the 64-bit value is divided into 8 bytes. Then, a logical OR operation is performed on each byte and the results are put into an encoder. Finally, the encoder interprets the results of the OR operations and places output values into processor registers which indicate whether or where a null byte was detected.

Abstract: A short circuit protection circuit which has a first short circuit protection circuit in parallel with a second short circuit protection circuit is disclosed. The first short circuit protection circuit includes a sense resistor and a comparator for detecting the short circuit, and a transistor and current source for turning off the low side driver when the short circuit is detected. The second short circuit protection circuit includes a current mirror, zener diode, transistor, and current source connected in series. The second short circuit protection circuit is in parallel with the first short circuit protection circuit. The second short circuit protection circuit accelerates the turn-off of the low-side driver with out affecting the stability of the circuit.

Abstract: A circuit and method for testing on-chip memory for a microprocessor or a microcomputer is disclosed. The memory test circuit includes an input register, an output register, an adder, and a sequencer to control the test process. The process includes receiving a simple communication protocol from the control unit to start the test, running a common memory test such as a checker board, AAAAh, 5555h and the like, and then storing the test results in an output register. The test circuit can include a bi-directional RESET signal means for disabling the system while the microprocessor or microcomputer runs its memory test.

Abstract: A method of obtaining a second function from keys on a standard QWERTY configured computer keyboard that have only a first function when struck individually is disclosed. First, the force applied by the user on the keyboard is measured and detected during a first period of time, and the normal level of force applied by the user is determined. Next, a second function actuating force which is greater than the normal force applied by the user is selected, and the force applied by the user on a keyboard during a second period of time is measured and detected. It is then determined whether the force applied by the user during the second period of time is greater than the second function actuating force, and if so, a computer operatively coupled to the keyboard is caused to perform a second function associated with the key. Otherwise, the computer performs the first function associated with the key.

Abstract: A data processing system includes a number of processing elements wherein each of the processing elements generates one or more condition signals, one or more memory elements associated with the processing elements for storing instructions and data associated with the processing elements, at least one register for storing a predicate associated with each of the processing elements and logic for comparing condition signals from each of the processing elements with a corresponding predicate to generate one or more branch test signals, and combination logic to provide a single take branch signal based on branch test signals and logic masks associated with each of the predicates.

Abstract: A method and apparatus for sharing distributed spares of a first array with a second array in a storage subsystem which included a number of storage arrays requires that at least a first array of the subsystem has available distributed spares, and that at least a second array has a same number of "rows" as the first array, for spare sharing. When a device failure occurs on the second array, the data and parity blocks of the failed device are reconstructed and placed in the spares of the first array, and the block addresses are appropriately remapped to the spares. Distributed spare sharing is possible because the first array is configured to include at least one spare region/row, and the second array will never lose a number of blocks greater than the common number of rows in the first array in a single device failure.

Abstract: A multi-mode time division multiplexing (TDM) interface circuit for interfacing between a serial data port and a data buffer is provided. The TDM interface circuit contains a transmitter and a receiver section. The circuit is programmable to operate in a variety of modes and is capable of supporting various multi-channel TDM interfaces as well as single channel analog interfaces. The circuit is programmable by writing a control word to a control register. In operation the circuit receives a frame synchronization signal, a gated bit clock signal, and a bit clock signal from the circuit with which it is interfacing on the serial data port. A base address input to a base address register provides up to 9 of the most significant bits of a data buffer address. A 12-bit counter is used to generate the remaining (least significant) bits of the data buffer address according to the control word in the control register.