Abstract: A firmware controlled microprocessor plugged into a printed circuit board received firmware signals from a control store mounted on the printed circuit board. The number of pins required for transferring firmware signals is reduced by time sharing pins with firmware signal required for the full cycle of operation and firmware signal required only during the second half of the cycle of operation.

Abstract: A multiprocessor data processing system includes a system management facility which controls the loading of each control store in the respective multiprocessor. The system management facility generates a sequence of commands which puts a processor in load mode, initializes a control store address register, transfers firmware words from a main memory to the control store, resets the load mode, starts a verify operation and checks the result of the verify operation.

Abstract: A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

Abstract: A data entry terminal includes a front panel, a shroud and a base plate. The terminal may be assembled as a desk mounted unit or a wall mounted unit, depending upon the orientation of the front panel to the shroud and base plate.

Abstract: A memory bank selection arrangement has a memory which is made up of smaller memories each of which has a number of banks of memory. First bits of a memory address are used by an address controller for addressing a location in a selected bank of a first of the smaller memories. The address may be incremented by the controller before being used to address a second of the smaller memories, and a carry output is generated when the first bits are incremented and there is a carry from the highest order bit thereof. The memory address also includes second bits which are input to an adder which increments the number represented by the second bits responsive to the carry out from the controller to compensate for the incrementation of said first bits. The incremented or unincremented number output from the adder is used by a selector to select a bank of the smaller memories so that they can be addressed using the incremented or unincremented first bits.

Abstract: In a computer terminal an electronic device allows the selection of the terminal address and baud rate via a DIP switch (Dual In-Line Package) located internally in the terminal or via external selection means by allowing the setting of signal line voltage level by means of jumper wires in a communication connector. To enable the external option, predetermined pins in the communications connector are jumpered to disable the DIP switch, whose settings are then ignored. By jumpering other predetermined pins in the communications connector, the signal line levels define the terminal address and the terminal baud rate.

Abstract: In a data processing system using a virtual memory addressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value. This invention minimizes the amount of logic required to back out of a software instruction after execution has begun and is faster than checking if all resources are present before any state change is made during the execution of a software instruction.

Abstract: The present invention relates to a computer system having a sequence controller for allowing direct memory access devices to access peripheral devices. The sequence controller allows the peripheral devices access to a global bus by providing access in a round-robin fashion. A microprocessor associated with the sequence controller and direct memory access has access to the global bus after each direct memory access. The amount of data allowed to be transferred in each direct memory access is restricted so that each device is equally serviced.

Abstract: A secure system includes a secure central processor unit, an input/output emulator, a number of commodity controller boards and a number of commodity memory boards. Apparatus in the secure CPU and firmware in the I/O emulator maintain the security of the overall system.

Abstract: Transparent cache memory for data processing system in which a central processing unit requests the read out of information contained in a working memory at a current address and immediately receives, without waiting, the requested information from the cache memory if the requested information is contained in the cache memory. Meanwhile the cache memory performs the reading and the storing into the cache, of information contained in the working memory at the address next following the current address, so as to advance a possible subsequent request of the central processing unit. If the requested information is not contained in the cache memory, the cache memory performs a double memory read in page mode at the current memory address and at the next following address, thus minimizing the occupation time of the memory. The double reading is performed only for those addresses which allow for page mode operation.

Abstract: The apparatus provides a secure input/output command system by the operating system generating a virtual input/output command including a virtual channel number, verifying that the user has authorization to access the processes and the device, and then generating a physical input/output command for transfer over a system bus to the device addressed by the physical channel number included in the command.

Abstract: A multiprocessor system includes a number of subsystems all coupled in common to an asynchronous system bus. Apparatus is included in the system bus interface logic of each processing subsystem to receive commands from the system bus and compare the interrupt priority level of the new command with the current command being executed. If the new command has a lower interrupt priority than the current command, then the subsystem sending the command will receive a not acknowledge response from the processing system. The apparatus is responsive to certain control signals from the new command to bypass the interrupt priority comparison logic and initiate an immediate interrupt regardless of the interrupt priority level of the current command being executed by the processing subsystem. The processing subsystem may also generate a command to itself via the system bus which requires the high speed interrupt.

Abstract: An address boundary detector is disclosed that functions with an arithmetic logic unit (ALU) in a computer processor while the ALU generates addresses by adding an offset or displacement to a base address. The detector monitors bits of addresses to determine whether a data item can be completely stored within the same block or page of memory as that addressed by the base address from which it was derived.

Abstract: Power recovery circuit for printer haivng printing elements actuated by electromagnets energized by a voltage VS available at a terminal. The circuit includes a voltage booster for generating a voltage HV higher than voltage VS at a node and a buffer capacitor charged by the voltage HV and connected between the terminal and the node, a connection between the electromagnets and the node for transferring the magnetic energy imparted to the electromagnets by the buffer capacitor for storing therein as capacitive energy, an inductor and a control switch, series connected between the node and the terminal, a recirculation diode connected between ground and the node common to the switch and the inductor, a voltage detector providing an enabling signal when voltage HV exceeds a predetermined level and a controlled oscillator, enabled by the enabling signal to generate a control signal which periodically switches the control switch on and off.

Abstract: A multiprocessor interrupt rerouting mechanism and method is disclosed for rerouting messages intended for a first processor to a second processor. In a fault tolerant computer system having several processors or LANs under the control of a single controller, when the controller completes a communication task requested by one of the processors, it will send an interrupt request to the requesting processor which then notifies the application process for which the communication task was performed, information regarding the status of the communication task. If for any reason the requesting processor being interrupted is inoperative or too busy to handle the interrupt request, the application process is then notified as to the status of the communication task by rerouting the interrupt request from the controller so that another processor can handle it.

Abstract: A universal peripheral controller is disclosed which uses DMA devices to provide access between a plurality of peripheral devices and other circuits within a computer system. A processor in the computer system recognizes a request from the controller to connect a peripheral via the system bus to another circuit connected thereto and establishes the connection. The processor then passes information to the controller and leaves the task of controlling the transfer of information to the DMA circuitry in the controller. The controller has a sequencer which examines each of the plurality of peripherals connected to it in a round robin operation to determine which peripherals are requesting a connection via the computer system bus to transfer information. The sequencer limits the time each peripheral can be connected to the system bus before servicing another peripheral request in order that all peripherals have equal access to the system bus.

Abstract: Data communication equipment, including relay modules and MODEMS, are mounted on etched back planes. Etched conductors transfer communication line signal pairs to the relay modules, from the relay modules to the MODEMS and from the MODEMS to an output connector. Ribbon cables plugged into the output connectors transfer the MODEM output signals to logic boards, which are plugged into an etched VME bus panel. CPU's plugged into the etched VME bush panel receive signals from and transfer signals to the etched VME bus.

Abstract: A data processing system includes a logical address to a physical address translator in an extended memory management unit. A 128 word memory stores task segment descriptor words which include a base address. A 16 word memory stores corresponding present bits to indicate if the addressed task segment descriptor is present in its memory. This arrangement allows a 128 word memory to be cleared in 16 memory cycles.

Abstract: A phase lock circuit for compensation for bit frequency variations of information read from a movable magnetic media including a phase comparator, a number of low pass filters, a decoupling element and variable frequency oscillator which is temperature compensated.

Abstract: A multifunction arithmetic indicator that is associated with and controlled by an arithmetic logic unit (ALU) to store standard arithmetic indicator information such as overflow, carry, arithmetic sign and all bits equal zero that are generated by the ALU when processing binary information. A control unit sends control signals to multiplexers in the multifunction arithmetic indicator that cause the selection of appropriate arithmetic indicator information from the ALU, no matter what the bit length of binary words being processed by the ALU. The selected indicator information is stored in a register for later use.