Abstract: A nested loop method for use in a memory test system to identify the width, depth, control line configuration, and part type of a synchronous memory, wherein bit patterns are retrieved from tables representative of a plurality of synchronous memories during execution of nested loops, from outer loop to inner loop, in the order of bank loop, RE loop, CE loop, CS loop, DQMB loop, and part type loop, and bits of an entry of a table occurring after a given entry are either a member of a superset or do not intersect bits of previous entries, and bits of an entry preceding the given entry are either a member of a subset or do not intersect bits of the given entry.

Abstract: An electronics control system for full color and monochrome flat panel displays which automatically accommodates video signals of numerous types and formats, whether interlaced, non-interlaced, composite, or video signals with separated sync signals. Display of such video signals on a wide selection of flat panel display systems also is accommodated. Incoming and output video rates are asynchronous. Plug-in modules allow the system to convert video signals of numerous types and modes for display on any flat panel display system. Images are both automatically, and under user control, up-sized and down-sized, positioned and oriented to fit the flat panel display being used. Color images are automatically reduced to grey scale monochrome when a monochrome flat panel display is being used. Push-pull A/D converter circuitry for digitizing color video signals is used to reduce cost while conserving power.

Abstract: Low cost and portable safety side shields for safety eye glasses which substantially protect eyes from harm caused by projectiles impacting the eye through open areas between the wearer's head and the eye glass frames. The side shields have no conducting parts, are resistant to impact, shattering, and chemical corrosion, and are securely fastened to the ear pieces of the eye glasses by a stretchable tube. The side shields fit inside of the ear pieces without touching the eye glass wearers face, and overlap portions of the top, side and front of the lens frames to prevent latitudinal, longitudinal and rotational slippage that would expose the eyes. An alternative embodiment provides further eye protection by partially overlapping the front of the lens frames in the area of the eye glass hinges.

Abstract: A two-port, coaxial, waveguide flowline sensor for transmitting TEM mode electromagnetic radio frequency signals through borehole fluids flowing through a longitudinal flowline cavity of the waveguide. The waveguide flowline sensor responds to changes in the conductivity, dielectric constant, and state of the fluid at high borehole temperatures and pressures. The sensitivity of the sensor is enhanced by impedance mismatches between two feedthrough waveguides comprising the ports of the sensor, and a flowline cavity waveguide.

Abstract: A current switch for borehole logging tools operating at high temperatures with high load currents, which includes a driver unit that responds to an input digital control signal by holding an output field effect transistor in a turn-off state until its gate electrode is fully charged before allowing the transistor to supply current to an inductive or acoustic load, and by effecting a rapid discharge of the gate electrode to turn the transistor off. A digital coupler is inserted between the source of the input digital control signal and the driver unit to electrically decouple the load current from the source. The effects of spurious noise contaminants including power spikes in the load, fly-back coupling, and Miller's capacitance thereby are minimized and a switching action with minimal transition time is achieved.

Abstract: A method and system for reducing overhead time required to search for memory blocks having programmed executable tasks. The system includes a memory control block queue for managing all memory control blocks, and an executable task control block queue which is a subset of the memory control block queue and which is regularly updated to include memory control blocks having pointers to only programmed currently-executing tasks and programmed executable tasks. When a search for executable tasks is initialized, only the executable task control block queue need be searched. Unnecessary overhead time needed to search memory control blocks having only unexecutable tasks is eliminated.

Abstract: A television receiver which can display images in different displaying forms on a display screen with an aspect ratio of 16:9 by controlling the video chroma processing circuit by the micro computer by operating the remote controlled signal acceptor or the key switch has memories. The first memory stores video control data for each displaying form and the second memory stores appointed data for designating predetermined video control data. When the displaying form is changed by operating the remote controlled signal acceptor or the key switch, the micro computer reads the video control data corresponding to the displaying form which is newly set from the first memory according to the appointed data of the second memory and changes, for example, the contrast characteristic in the signal processing circuit according to the read data.

Abstract: A Local Area Network (LAN) is disclosed in which each node includes means for receiving clock signal information from an external network, which may by way of example be another LAN or a wide area network (WAN), and for generating therefrom clock signals for each node of the local network to accommodate synchronous information exchanges with the external network. Any one of the nodes of the local LAN network may act as a Control Node, and any one of the remaining nodes upon instruction from the Control Node may act as a primary Transmission Node for generating clock signals based upon the external network clock signals for all of the nodes of the local LAN network.

Abstract: A cap inserted into a wafer process tube for vertical furnaces is provided with exhaust flow normalizing means which can control or prevent variations in exhaust flow rates in the process tube, and thereby control variations in thickness of wafers subjected to film forming and annealing.In the alternative, an annular hollow ring is hermetically sealed around an outer circumferential surface of the process tube. An exhaust pipe is connected to the hollow annular ring. Gas communication holes are formed in the wall of the process tube to accommodate the flow of gas between the tube and the hollow annular ring. The spacing and cross-sectional area of the communication holes are such as to equalize flow resistance circumferentially around the cap. In-plane variations and wafer to wafer variations in thickness and quality of wafers subjected to film forming and annealing thereby are reduced and controlled.

Abstract: A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein an ISL unit may be reconfigured to reallocate communication bus resources without incurring excessive software overhead time losses.

Abstract: A logic control system in a video display terminal is disclosed for synchronizing the operation of dual, asynchronously operating CRT control unit semiconductor chips to accommodate a substantially increased number of visual attributes per display row with minimal effect on data character transfer rates.

Abstract: An automatic purge control for a banknote dispensing system including an operator panel having a keyboard for initiating transaction requests, a dispensing chamber adjacent to the panel for receiving banknotes dispensed in response to an operator request, a lockable access door to enable the operator to gain access to the chamber to remove dispensed notes, and a tiltable platform positioned within the chamber for discharging dispensed notes from the chamber under predetermined purge conditions detected by a microprocessor within the system. The microprocessor calls for a purge operation when it has been determined that the operator has either failed to remove dispensed notes or has left notes within the chamber. Interlocks are provided on the purge apparatus for inhibiting continued operation of the dispensing system if a purge cycle is improperly executed.

Abstract: A badge reader logic system is provided for receiving binary coded information read from a badge, card or other recording medium having data encoded thereon by means of bistable magnetic wire patterns, and reformatting such binary coded information into a two-dimensional data matrix row and column format for processing by a local controller. The binary coded information further is interrogated in time relation with logic signals received from sensors placed along an insertion path of the badge into the badge reader to detect unauthorized badges, incorrect badge orientations and other error conditions.

Abstract: An automatic cash depository having a tiltable feeding mechanism which receives an inserted deposit envelope and delivers it to a collection bin. Controls are provided for maintaining the feeding mechanism in a first position representing a blind feed path which does not present access to the collection bin. After the deposit envelope has fully entered the feeding mechanism and the insertion slot has been closed by a rotatable bolt closure, the control tilts the feeding mechanism and causes the envelope to be delivered to the collection bin.

Abstract: A hardware/firmware communication line adapter for interfacing a communication processor to a broadband high level data link communication channel. Transmit and receive data and control characters received either from the processor or from a communication channel device are processed under the control of the adapter firmware to effectuate CRC checking, byte size control, extended and variable field format control, partial last byte control, and block transfer control functions on the transmitted/received data stream. First-in-first-out (FIFO) buffer memories are employed in the transmit circuits to queue a frame of transmit data and control characters at the adapter whereby the communication processor/adapter interface control is simplified. Similarly, a FIFO buffer is employed in the receive circuits to reduce the frequency of receive interrupts and to enable block transfer of received data to the processor.

Abstract: A hardware/firmware control system is disclosed for accommodating the concurrent bi-directional transfer of information between a communications channel such as a telephone line and a communications processor in a data processing system.

Abstract: A logic control system for a video display terminal is disclosed for accommodating vertically and horizontally varying entry points to a video memory to acquire first character bytes of rows of video information for display on a CRT screen. Dynamically changeable display page snapshots of the video memory, and the formation of display pages from randomly located rows of video information within the video memory are thereby provided.

Abstract: A data communication simulator system wherein the basic operational conditions of a bit and byte synchronized data network may be simulated by generation of a bit timing signal, a byte timing signal, data signals, and control and status indication signals. Manual as well as automatic testing modes are provided, the manual mode including a signal stepping control arranged to enable either full or half cycle operation.

Abstract: A logic control system is disclosed for verifying the operability of memory and non-memory data and control paths in both local and remote intersystem link (ISL) units electrically interconnecting a local and remote communication bus in a data processing system. The data processing system may include two or more communication busses each pair of which are electrically interconnected by twin ISL units. The control logic architecture accommodates the receipt of a test mode command from a CPU on a local bus to initiate a test mode operation wherein the memory and non-memory data and control paths of both the local and the remote ISL units are excerised while on-line, and binary coded information received from the local bus is passed through the ISL units, onto the remote bus, and returned to a local bus memory resource for verification. No remote bus resources are used or affected, and the remote ISL unit shall ignore any communications received from any other data processing unit on the remote bus.