Abstract: In the plating of articles, particularly the filling of via-holes (16) in the manufacture of semiconductor devices, a catalyst, for example palladium, is incorporated throughout the body of material (12) to which plating is to be effected, as compared with activating just the surface of the body.

Abstract: Isolation and passivation structures are formed in a single step, after transistor fabrication, by CVD deposition of a layer of oxide or BPSG over the wafer. The passivation/isolation layer overfills trenches formed for isolation and covers the patterned transistor device The layer is subsequently planarized by chem-mech polishing. With only one deposition step involved, to form both isolation structures and a passivation layer, there is significantly less strain on the thermal budget. Process and product by process are disclosed.

Abstract: Improvements to self-replicating duplex forms are disclosed. Generally, a single sheet of paper is divided into original and copy panels by fold line, and carbonless coatings are applied to the panels so that information entered on the two, front and back surfaces of the original panel are reproduced on the two surfaces of the copy panel.(Group 1) An endorsable carbonless CB coating is applied to the original panel, either at the mill or on-press. A carbonless CF coating is applied to the copy panel so that the coated copy panel is substantially the same thickness as the coated original panel. Specific areas for filling out information on the original panel are offset, from front-to-back, and methods of checking this offset are disclosed. The copy panel is tinted a dissimilar base color from the original panel.(Group 2) The original and copy panels can be formed separately, and joined into a single "virtual" sheet.(Group 3) The original and copy panels can be formed of a single sheet of CF C2S paper stock.

Abstract: A technique for at-speed testing of the core logic of a digital integrated circuit device is disclosed. Test patterns are applied to the circuit inputs while applying a "burst" of three clock pulses followed by a "dead cycle"to the pipeline stages between the input logic, the core logic and the output logic. During the dead cycle, changes in the outputs of the device are observed during the dead cycle. Subsequently, a second burst of clock pulses, offset from the first burst, and followed by a dead cycle, is applied with re-initialized test patterns, and the outputs are observed during the dead cycle. Subsequently, a third burst of clock pulses, offset from the first and second bursts, and followed by a dead cycle, is applied with re-initialized test patterns, and the outputs are observed during the dead cycle. The results of the three iterations of the test are stored and merged to provide a valid indication of the performance of the device with a free running clock.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.

Abstract: A system for interactive, design and stimulation of an electronic circuit allowing a user to design a circuit by graphical entry and to view full or partial simulation and design results, simultaneously, on a single display window. The user is able to define the form of a display of speed, delay, loading, symbols, simulation input and/or output values on each node and any path of the design. Simulation may be user-defined or other process time.

Abstract: A radiation hardened NMOS transistor structure suited for application to radiation hardened CMOS devices, and the method for manufacturing it is disclosed. The new transistor structure is characterized by "P" doped guard bands running along and immediately underlying the two bird's beak regions perpendicular to the gate. The transistor and the CMOS structure incorporating it exhibit speed and size comparable to those of conventional non-rad-hard CMOS structure, relatively simple manufacturing, and excellent total-dose radiation hardness.

Abstract: A glass passivation layer is deposited, densified and polished. Thereby an underlying wafer containing substantially defined devices is exposed to a temperature cycle that is sufficient for densification of the glass, and no more. Reflow and its attendant additional temperature cycle are thereby avoided, allowing for smaller, faster devices to be fabricated. Increased control over the ultimate thickness of the glass layer is also provided.

Abstract: A box is folded from a flat blank of sheet material. The flat blank of sheet material has a bottom portion, two side walls correspondingly connected via folds to first opposing edges of the bottom portion, and two end walls correspondingly connected via folds to second opposing edges of the bottom portion. The second edges extend perpendicular to the first edges. The end walls are of "double-wall" design, including inner and outer wall portions. Connecting portions are provided, with each connecting portion connected to intersecting edges of a side wall and a corresponding inner wall portion of an end wall and symmetrically foldable about a fold diagonally extending from a corner of the bottom portion such that in an erected state of the box the connecting portions are foldedly received between the corresponding inner and outer wall portions of each end wall.

Abstract: A magnet is disposed in proximity to an un-lidded semiconductor package being assembled. When a ferrous lid is placed over the package opening, the magnetic field holds the lid in place, and also holds the package on an assembly boat carrying the package through an oven for hermetic sealing.

Abstract: Wells are formed in an external surface of a semiconductor device package body. Capacitors are disposed within the wells at least partially, and preferably fully within the body. Cleaning channels are formed underneath the capacitors, for removing residual flux and/or solder.

Abstract: A pipelined floating point multiplier is disclosed having the capability of interleaving floating point multiplication with iterative floating point operations (calculations), such as division and square-root taking, by making use of idle stages (pipeline bubbles). This is accomplished with minimal additional circuitry over that required for conventional floating-point multipliers, and does not adversely affect the speed of iterative calculations. Method and apparatus are disclosed.

Abstract: A capacitor is disposed within a semiconductor device assembly atop a plastic layer pad, beneath which passes a pair of leads connected to a semiconductor device. The capacitor is connected to the pair of leads, such as by soldering, spot welding or conductive epoxy through cutouts in the pad. In one embodiment, the cutouts extend into the pad from inner and outer edges thereof. In another embodiment, the cutouts are holes through the pad. A plurality, such as four, capacitors are conveniently disposed atop a corresponding plurality of pads, and are connected to a corresponding plurality of pairs of leads within the semiconductor device assembly. By positioning the capacitor(s) as closely to the semiconductor device as possible, the efficacy of the capacitor(s) is maximized. Method and apparatus are disclosed.

Abstract: A single sheet of paper is delineated into two or more panels, and is coated with carbonless treatment so that information entered on both sides of one of the panels is reproduces onto the other panel(s). The use of carbonless CB and CF, and carbonless SC coatings is disclosed. Methods of making and using the carbonless paper are also disclosed.

Abstract: In a leadframe supporting a semiconductor device, the tiebar adjacent the mold gate is kinked, or cut and bent, to form a baffle shielding bond wires connecting the semiconductor device to the leadframe from damage by a jet of incoming molding compound. Whether kinked or cut/bent, the baffle extends out of the plane of the leadframe so as to be disposed more-or-less directly in front of the gate.

Abstract: A digital filter, and more particularly a digital filter such as a transversal filter, is disclosed which is comprised of digital filter modules and provided with a function to detect the occurrence of anomalies such as overflow (a state in which excessively large or small absolute values exceeding an allowable limit are produced during arithmetic operations).

Abstract: A first heat sink disposed immediately below and closely adjacent a semiconductor chip in a semiconductor chip assembly is disclosed. The heat sink is a flat metallic or ceramic shim. A second heat sink disposed immediately above and closely adjacent the semiconductor device is disclosed. The second heat sink preferably has a flat surface forming an exterior surface of the semiconductive device assembly . In one embodiment, the second heat sink has pedestals resting atop a plastic layer in a tape-like structure within the semiconductor chip assembly. In a second embodiment, the second heat sink includes an add-on portion that is external to the semiconductor chip assembly. The first heat sink is particularly well-suited to applications where the semiconductor chip assembly is mounted to a thermal mass. The second heat sink is particularly well-suited to applications where air cooling is available.

Abstract: A technique for pinpointing and analyzing failures in complex integrated circuits is disclosed. A device-under-test (DUT) is powered up. Using Liquid Crystal (LC) or Photo-Emission (PE) techniques, leakage sites are identified. The leakage sites are associated with suspect circuit elements on the DUT, and candidate I/Os associated with the suspect failing elements are selected for subsequent testing. Using the candidate I/Os, a truncated set of test vectors is created, and applied to the DUT. While the DUT is running the truncated set of test vectors, the suspect elements are rigorously probed to identify failing elements. SEM images are preferably viewed simultaneously. In this manner, a log of failing elements is derived, for circuit or process re-design.

Abstract: A periodic sequence of signals is intiated and provided to a counter. During this time, a pulse (PULSE) is generated. Upon reaching a terminal count the pulse is terminated. The pulse is provided to a delay element which receives at its input a signal (s) entering, processed within or exiting a semiconductor device. The pulse and periodic sequence of signals are initiated by an edge detector detecting a trigger signal (TRIGGER), which may be the signal (s) being delayed. The sequence of signals is generated by a circuit element, such as a ring oscillator, and the periodicity of the sequence of signals is related to the inherent switching speed of the semiconductor device technology. A plurality of delay circuits are provided in a semiconductor device for individually delaying a plurality of signals entering, processed within and exiting the device. A library of delay circuits may pre-designed, and stored for implementation, as needed, in semiconductor devices.

Abstract: A semiconductor device is mounted to one face of a printed wiring board (PWB). A heat sink is mounted to an opposite face of the board, opposite the die. The heat sink has a plurality (at least four) "nubs" protruding through a like plurality of holes in the board in the region of the die. In this manner, the nubs conduct heat from the die, through the board, to the heat sink. Preferably, the nubs are sized and shaped to press fit into the holes. Preferably, the holes are plated. Preferably, the heat sink is formed of powdered metal, such as aluminum, copper or a copper/tungsten alloy. The die is attached to the board by any suitable method, such as epoxy and wire bonding, tape automated bonding (TAB), etc. After the heat sink is mounted to the board, the die is encapsulated with resin. A multi-chip module using the novel heat sink structure is also disclosed.