Abstract: A method, apparatus and system are disclosed for redistributing memory allocation to portions of dynamic random access memory (DRAM) and dual in-line memory module (DIMM) devices that are underutilized, in order to balance memory usage more evenly amongst active devices so as to limit the amount of power and the thermal load consumed by an individual memory component. The disclosed method, apparatus and system are capable of identifying and tracking memory usage to minimize power consumption in a way that lessens the detrimental effects of “throttling” or reduced power modes for memory devices.

Abstract: A method, apparatus and system are disclosed for a Peripheral Component Interconnect (“PCI”) Express connection device that supports use of device bus widths different than the size of the connector in communication of data processing, addressing and/or control signals between electronic and/or computer devices. Specifically, a PCI Express connector is disclosed that allows installation of a PCI Express adapter having a larger bus width than that of the connector itself, by including an opening (or “notch”) in at least one end of the connector to physically accommodate the larger dimension(s) of the adapter.