Patents Represented by Attorney Gibb I.P. Law Firm, LLC
  • Patent number: 8122395
    Abstract: A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventor: Kai Di Feng
  • Patent number: 8120175
    Abstract: A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca
  • Patent number: 8112063
    Abstract: The present invention deals with a method and system for routing a call in a mobile communication network. The method comprises receiving a message by a caller prevailing network corresponding to a caller from a callee home network corresponding to a callee, if the callee is roaming. The message is received in response to the call being initiated by the caller for the callee. The message can comprise a redirection information corresponding to the callee in roaming. The method further comprises solving a predefined criterion for routing the call based on the redirection information in the message and connecting the call based on solution of the predefined criterion.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Pankaj Kankar, Sunil Chandra, Sougata Mukherjea
  • Patent number: 8105901
    Abstract: A method deposits an undoped silicon layer on a primary layer, deposits a cap layer on the undoped silicon layer, patterns a masking layer on the cap layer, and patterns the undoped silicon layer into silicon mandrels. The method incorporates impurities into sidewalls of the silicon mandrels in a process that leaves sidewall portions of the silicon mandrels doped with impurities and that leaves central portions of at least some of the silicon mandrels undoped. The method removes the cap layer to leave the silicon mandrels standing on the primary layer and performs a selective material removal process to remove the central portions of the silicon mandrels and to leave the sidewall portions of the silicon mandrels standing on the primary layer. The method patterns at least the primary layer using the sidewall portions of the silicon mandrels as a patterning mask and removes the sidewall portions of the silicon mandrels to leave at least the primary layer patterned.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Toshiharu Furukawa
  • Patent number: 8106462
    Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: January 31, 2012
    Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc., Infineon Technologies North America Corp., Chartered Semiconductor Manufacturing Ltd.
    Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
  • Patent number: 8100399
    Abstract: A printing device has at least one printing engine, at least one media path adjacent the printing engine, and a paper tray adjacent the media path. The paper tray stores media and supplies the media to the media path. Further, at least one sheet guide is attached to the paper tray, and at least one rectangular member is attached to the sheet guide. The rectangular member has a sheet guide opening, and the sheet guide opening attaches to the sheet guide. The rectangular member has a first planar surface that is coplanar with a second planar surface of the sheet guide. Also, the first planar surface is at least twice the two-dimensional size of the second planar surface. The first planar surface and the second planar surface contact media stored within the paper tray.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: January 24, 2012
    Assignee: Xerox Corporation
    Inventor: Keith L. Willis
  • Patent number: 8103388
    Abstract: Disclosed are a power management system and associated method that not only initiate a “greenout” to avoid the negative impact of high loads (i.e., to avoid high power cost, negative environmental impact, brownouts, and ultimately blackouts), but can also predict the initiation of such a “greenout”. Predicting the initiation of a “greenout” and communicating the prediction to one or more of the various electronic devices connected to the power grid allows the electronic device(s) to take preparatory action to avoid and/or limit any negative impact that may be caused by the “greenout”.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kenneth J. Goodnow, Stephen G. Shuma, Peter A. Twombly
  • Patent number: 8097474
    Abstract: Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s).
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Theodoros Anemikos, Ezra D. B. Hall, Sebastian T. Ventrone
  • Patent number: 8095880
    Abstract: A method provides, as part of a computer administration system, an administration interface that can operate on almost any computerized device that has a user interface. The computer administration system manages components of a computer system and the administration interface is operable to configure the components and to provide dynamic performance and configuration information of the components to the user as the components operate. The method provides a “commentary input” area on the administration interface while providing the performance and configuration information of a specific component or a set of components. Thus, the method can receive comment(s) about the specific component(s) of the computerized system in the commentary input area. When this occurs, the method stores the comment(s) in a data store in a manner that associates the comment(s) with the specific component(s) that was being monitored.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: January 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Andreas Dieberger, Eben M. Haber, Eser Kandogan, Gilly Leshed
  • Patent number: 8095918
    Abstract: A software development apparatus for developing application software based on an object model that requires security in a web service application is provided. The software development apparatus includes a display unit that displays, in a class diagram of the application software, security annotation for adding security requirements for a service, input means for inputting the security annotation, transforming means for transforming the class diagram into a configuration model based on a markup language, and configuration-file creating means for creating a configuration file based on a markup language by serializing the configuration model based on a markup language. The security annotation includes the security requirements and a token class of a security token that is a certificate for declaring identity of a client to a server.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: January 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Fumiko Satoh, Yuichi Nokomuru, Kouichi Ono
  • Patent number: 8095902
    Abstract: A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for the critical parameters. Further, methods herein include designing a ring oscillator to have stages, each of the stages measuring only one of the critical parameters. This ring oscillator is then included within an integrated circuit design and associated design structure. The embodiments herein produce an integrated circuit according to this integrated circuit design and operate the ring oscillator within the integrated circuit to measure the critical parameters of the integrated circuit and produce test results. These test results are output to determine whether the test results are within the acceptable limits.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: January 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anthony W. Fazekas, Kenneth Mon Ngai, Joseph J. Oler, Jr.
  • Patent number: 8095524
    Abstract: A system for integrating personal information search and interaction on web and desktop applications comprises enabling a user-interface (UI) component of an application for the entry of a query the UI component associated with context information. Entry of the query based on a natural language grammar is parsed to determine at least one natural language element. Element types associated with each natural language element are generated. A query command from a command list based on the natural language elements, the element types and the context information is interpreted. The query with arguments based on the natural language elements of the natural language query are executed to determine a result. The transformed result is output through said UI component by replacing said result for said query wherein outputting said transformed result comprises automatically adding email addresses, attachments and maps to said UI component.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: January 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Eser Kandogan, Seonho Kim
  • Patent number: 8087823
    Abstract: A structure has a heat dissipating feature, an internal temperature measurement device, and a memory. The structure generates heat as power is supplied to the structure, and a threshold voltage of the internal temperature measurement device changes as the temperature of the temperature measurement device changes. The embodiments herein establish a linear relationship between temperature and threshold voltage by heating the structure to a first temperature and recording a first threshold voltage, and then heating the structure to a second temperature and recording a second threshold voltage. From this, the embodiments herein calculate a linear relationship between temperature and threshold voltage. Further, the embodiments herein can calculate the temperatures of the structure based only upon the linear relationship and threshold voltages measured from internal temperature measurement device.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: January 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Francois Aube, Timothy M. Curtin, Matthew S. Grady, Thomas P. Scanlon, Eric N. Smith
  • Patent number: 8090762
    Abstract: Embodiments herein present a system, method, etc. for an efficient super cluster implementation for solving connected problems in a distributed environment. More specifically, the system adapts computing latency to communication latency, wherein the system comprises VPPs wrapped within OCW layers. The VPPs represent a subset of an overall computer task; and, the OCW layers are adapted to enclose the VPPs. Specifically, the number of OCWs that enclose a VPP correspond to the number of computing iterations that may be locally executed by the VPP during an inter-VPP communication cycle. In addition, each VPP comprises collections of OPCs, wherein the OPCs comprise data, methods, and pointers to neighbors. The OPCs are indexed separately based on whether the OPC is part of an OCW layer.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: January 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Robert G. Deen, James H. Kaufman, Tobin J. Lehman
  • Patent number: 8087023
    Abstract: The invention provides a system/method of processing client requests over a computer network of hosts, that includes creating persistent containers in the hosts, creating objects in the containers, grouping the containers into grid container arrays, grouping objects within containers that are within a single grid container array into grid object arrays, creating one micro scheduler for each grid container array, dividing each of the client requests into a plurality of tasks, and assigning groups of the tasks to the microschedulers, wherein the microschedulers assign individual tasks to the objects. The invention assigns the microschedulers additional groups of tasks as the microschedulers return groups of completed tasks. The method can also include passing the client requests through gateways to multiple grid services schedulers.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: James Robert Harold Challenger, Marcos Novaes
  • Patent number: 8086988
    Abstract: Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Nathan Buck, Howard H. Chen, James P. Eckhardt, Eric A. Foreman, James C. Gregerson, Peter A. Habitz, Susan K. Lichtensteiger, Chandramouli Visweswariah, Tad J. Wilder
  • Patent number: 8083958
    Abstract: Disclosed are embodiments of a lithographic patterning method that incorporates a combination of photolithography and self-assembling copolymer lithography techniques in order to create, on a substrate, a grid-pattern mask having multiple cells, each with at least one sub-50 nm dimension. The combination of different lithographic techniques further allows for precise registration and overlay of the individual grid-pattern cells with corresponding structures within the substrate. The resulting grid-pattern mask can then be used, in conjunction with directional etch and other processes, to extend the cell patterns into the substrate and, thereby form openings, with at least one sub-50 nm dimension, landing on corresponding in-substrate structures. Once the openings are formed, additional structures can be formed within the openings.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wai-Kin Li, Haining S. Yang
  • Patent number: 8080465
    Abstract: Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and absorption characteristics can be balanced by incorporating an additional reflectance layer into the wafer structure above the substrate. Methods of forming a semiconductor structure begin by forming a substrate, forming an insulator layer on the substrate, and forming a first film on a first portion of the insulator layer.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8080485
    Abstract: A method of forming a semiconductor structure comprises providing a substrate and forming an insulator layer on the substrate. A first film is formed on the insulator layer. Thus, the first film can correspond to a device region of the semiconductor structure. A second film, comprising a second material that is different from the first material, is also formed on the insulator layer adjacent to the first film. The second material can comprise an isolation material (e.g., an oxide and/or nitride material) and can, for example comprise the same dielectric material as the insulator layer (e.g., silicon dioxide). The second film can correspond to an isolation region (e.g., a shallow trench isolation region) of the semiconductor structure. The second film is specifically formed with a first section having a first thickness and a second section having a second thickness that is different from the first thickness.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8076190
    Abstract: A semiconductor device and a method of fabricating a semiconductor device is disclosed, the method comprises including: forming etching an oxide layer to form a pattern of parallel oxide bars on a substrate; forming nitride spacers on side walls of the parallel oxide bars, with gaps remaining between adjacent nitride spacers; forming silicon pillars in the gaps; removing the nitride spacers to form a plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: December 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: Howard H. Chen, Louis C. Hsu, Jack A. Mandelman, Chun-Yung Sung