Abstract: A semiconductor device includes interconnected conductor lines comprising a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines are formed on the top surface of the lower ILD layer surrounded by an insulator formed on the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and it is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on a upper level. Each has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer is formed below the intermediate conductor to electrically insulate and separate the intermediate conductor lines from the lower conductor lines.

Abstract: An implanting method forms high-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at the ESDPD, without covering the center region under the drain contact (DC). The ESDI LDD concentration and doping profile are deep to contain drain diffusion. Regions with the ESDI have a high junction breakdown voltage (JBV) and a low junction capacitance. After forming gate sidewall spacers, implant high doping concentration ions into active D/S regions forming a shallower doping profile of the D/S diffusion. The drain has a JBV as without this ESDI, so the ESD current (ESDC) is discharged through the center junction region under the DC to bulk, far from the ESDPD surface channel region. The ESDPD sustains a high ESD level. The original drain JBV of an MOS with this ESDI method is unchanged, i.e.

Abstract: A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the reticle mask by removing a set(s) of the features that are juxtaposed to form hollow polygonally-shaped clusters with a gap in the center. Form unexposed resist on the workpiece. Load the workpiece and the reticle mask into the stepper. Expose the workpiece through the reticle mask. Reposition the workpiece by a nanostep. Then expose the workpiece through the reticle mask after the repositioning. Test whether the plural exposure process is finished. If the result of the test is NO the process loops back to repeat some of the above steps. Otherwise the process has been completed. An overlay mark is produced by plural exposures of a single mark. A dead zone is provided surrounding an array region in which printing occurs subsequent to exposure in an original exposure.

Abstract: A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.

Abstract: A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first dopant type, is separated by an interface from a well region surrounding the upper and central portions of the DT that are doped with an opposite dopant type. A source/drain region formed at the top of the cell is doped with the first dopant type. A node dielectric layer that covers the sidewalls and bottom of the lower and central portions of the DT is filled with a node electrode of the capacitor, doped with the first dopant type, fills the space inside the node dielectric layer in the lower part of the DT. Above a recessed node dielectric layer a strap region space is filled with a buried-strap conductor. An oxide (TTO) layer is formed over the node electrode and the buried-strap in the DT.

Abstract: A multilayer thin film via landing pad structure includes a thin film conductor structure with a recessed landing pad formed between an upper layer of polyimide dielectric and a lower layer of polyimide dielectric. A multilayer thin film via landing pad structure is formed on a lower layer of dielectric having a top surface. A depression is formed in the top surface of the lower layer of dielectric. The depression has a bottom within the lower layer. A recessed landing pad comprising a conductor is formed in the depression on the surface of the lower layer of dielectric. A conductor line is formed on the lower layer of dielectric in contact with the recessed landing pad. An upper layer of dielectric is formed over the lower layer of dielectric, the thin film conductor line and the recessed landing pad. A conductive via is formed extending through the upper layer of dielectric into contact with the recessed landing pad.

Abstract: A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.

Abstract: A split gate EEPROM memory device formed on a doped silicon semi-conductor substrate starting with an initial oxide layer with an undoped first polysilicon layer formed thereon. A polysilicon oxide hard mask over the undoped first polysilicon layer for use in patterning the initial oxide layer and the undoped first polysilicon layer which are then etched to form a floating gate electrode stack from the undoped first polysilicon layer and the initial oxide layer on the substrate. Then form a tunnel oxide layer and a doped polysilicon and pattern them into control gate electrode stack, with the control gate electrode stack being located in a split-gate configuration with respect to the floating gate electrode stack.

Abstract: To allocate products for machines on a manufacturing line, provide a standard test time. Minimize total test time with respect to production scheduling. Form a supply demand matrix table for products and machines for product allocation. Find the grid location with minimum testing time. Provide maximum time allocation from a machine at the corresponding position on the matrix table. Determine the grid location with the next minimum testing time. Loop back to provide a maximum allocation of remaining time from the corresponding machine and repeat looping back until no demand is left. Find need for an optimum testing process by testing whether only one machine can test the product and no quantity is allocated to a machine. If YES branch to calculate utilization per machine. If NO, decide whether NCOL+NLIN−1=NVB. If YES perform optimum testing. If NO, branch to calculate machine utilization per machine.

Abstract: A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold.

Abstract: A capacitor structure is formed on a semiconductor substrate to provide split voltages for semiconductor circuits. An active area is formed in the substrate serving as a lower capacitor plate for a bottom capacitor. A thin dielectric layer and field oxide regions are formed on the substrate, and the dielectric layer is covered with a capacitor plate over the active area to complete the bottom capacitor. A thick dielectric layer is formed over the device and a via is formed through the thick dielectric layer to the upper capacitor plate. A second lower plate is formed for a top capacitor. An inter-layer dielectric layer is formed over the second lower plate. An upper capacitor layer is formed over the inter-layer dielectric layer to form a top capacitor with a different capacitance value from the bottom capacitor. The value of the capacitance can be varied by selection of the permittivity and/or thickness of the dielectric layer and by variation of the effective plate area of the top and bottom capacitors.

Abstract: A system for managing quality control in a manufacturing plant for processing lots of work in process (WIP) for at least one product, comprises a manufacturing process which includes a manufacturing executive system (MES) which provides inspection data to a statistical process control (SPC) database, and an SPC analyzer for analyzing the inspection data and providing a sampling rate rule output to a sampling rate database. A server supplies the sampling rate rule to the MES. The MES tests a condition as to whether a lot of WIP should be sampled. If the condition is met, then provide an inspect control signal for inspection to the plant for inspecting the lot. If the condition is not met, then branch away from the control signal to provide an alternative control signal to pass on to the next process step in the plant.

Abstract: To obtain data pertaining to the surface characteristics of a sample, a control method adjusts a tilted rastered E-beam to in SEM to a first/next tilt condition and navigates the SEM-beam to a sample site. The system performs a fine alignment step. Then the system scans a region of a sample to acquire a waveform. The system analyzes the waveform to determine the DESL value for each edge of interest. The system tests whether there is sufficient information available for each structural edge. If NO, the system repeats the above steps starting by changing the value of the tilt angle to acquire another waveform. If YES, the system determines the height and sidewall angles for each structural edge. Then the system reports the sidewall angle and the structure height for each edge of the structure under test. The system then corrects the critical dimension measurement determined from 0 degrees tilt scanning.

Abstract: An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.

Abstract: A CMOS charge pump circuit with diode connected MOSFET transistors is formed with asymmetric transistors which preferably have halo source region implants with a forward threshold voltage (VthF) and with a reverse threshold voltage (VthR), with the forward threshold voltage VthF being substantially larger than the reverse threshold voltage VthR. Preferably, the halo source regions are super halos. An SRAM circuit with pass transistors and pull down transistors includes pass transistors which comprise super halo asymmetric devices.

Abstract: A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periphery of the carrier. There is an upper adhesion layer shaped as a matching an upper frame facing downwardly from the cover towards the lower frame. Above the soft lower frame is a lower metal adhesion layer. Between the upper frame and the lower adhesion layer is a solder layer which has been heated to seal the cover to the chip carrier. The soft frame can include a channel through which a metal to metal via-seal is formed by the lower metal adhesion layer and the solder through the channel through the soft layer or there can be a lateral extension of the lower metal adhesion layer to a distal location beyond the periphery of the soft lower frame.

Abstract: An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack.

Abstract: A method and a apparatus are provided for operating an E-beam system including an E-beam source for generating an E-beam directed along a column axis and an electrode aligned with the column axis direct the E-beam towards means for measuring the E-beam. A signal proportional to leakage current emitted from the E-beam is generated. When the result of a comparison with a desired value is excessive, an excess leakage signal is generated. The excess leakage signal can be provided as an emergency output signal and/or produce an OFF signal for stopping production of the E-beam by turning OFF voltage/power sources for producing the E-beam in response to the excess leakage signal. Preferably, a filament is heated by an electric current and a cathode is bombarded with electrons from the filament to produce the E-beam. Then a filament control signal is employed for controlling the filament heating current.

Abstract: A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the reticle mask by removing a set(s) of the features that are juxtaposed. Form unexposed resist on the workpiece. Load the workpiece and the reticle mask into the stepper. Expose the workpiece through the reticle mask. Reposition the workpiece by a nanostep. Then expose the workpiece through the reticle mask after the repositioning. Test whether the plural exposure process is finished. If the result of the test is NO the process loops back to repeat some of the above steps. Otherwise the process has been completed. An overlay mark is produced by plural exposures of a single mark. A dead zone is provided surrounding an array region in which printing occurs subsequent to exposure in an original exposure. Stepper-framing-blades are moved over the dead zone to prevent additional exposures after an initial exposure.

Abstract: A capacitor is formed in a trench in a well/substrate doped with a first polarity. A dielectric isolation collar formed on trench sidewalls is recessed below the trench top and is spaced from the trench bottom. Therebelow, a counterdoped plate electrode region surrounds the trench and a node dielectric covers the exposed sidewalls. A counterdoped conductive buffer layer or region covers the node dielectric. A conductive, lower diffusion barrier covers the buffer. A first polarity doped node conductor, which is formed over the lower diffusion barrier, is covered by a conductive, upper diffusion barrier. A counterdoped cap covers the upper diffusion barrier. A counterdoped strap region formed by outdiffusion into the substrate is juxtaposed with the edge of the cap.