Abstract: Power semiconductor devices having overlapping floating field plates include a primary field plate and a plurality of floating field plates which are formed on an electrically insulating region and capacitively coupled together in series between an active region of a power semiconductor device and a floating field ring. Preferably, the capacitive coupling is achieved by overlapping at least portions of the floating field plates. According to one embodiment, a power semiconductor device comprises a semiconductor substrate having a first region of first conductivity type therein extending to a face thereof and a second region of second conductivity type in the first region of first conductivity type and forming a P-N junction therewith.

Abstract: Power semiconductor devices having discontinuous emitter regions therein include a semiconductor substrate containing therein a collector region of second conductivity type, a buffer region of first conductivity type which forms a first P-N junction with the collector region and a drift region of first conductivity type which forms a non-rectifying junction with the buffer region. A base region of second conductivity type is also provided in the drift region and forms a second P-N junction therewith. In addition, a base contact region of second conductivity type is provided in the base region of second conductivity type. The base contact region typically has a much higher second conductivity type doping concentration therein than the base region. A preferred emitter region is also provided in the substrate. This preferred emitter region comprises an emitter contact region which is entirely surrounded in the substrate by the highly doped base contact region and a carrier emitting region.

Abstract: Methods of forming power semiconductor devices having insulated gate bipolar transistor cells and freewheeling diodes cells therein includes the steps of forming an array of emitter regions of second conductivity type (e.g., P-type) in a cathode layer of first conductivity type (e.g., N-type) and then forming a base region of first conductivity type on the cathode layer. An insulated gate electrode(s) pattern is then formed on a surface of the base region and used as an implant mask for forming interleaved arrays of collector and anode regions of second conductivity type in the base region. An array of source regions of first conductivity type is then formed in the collector regions, but not the anode regions, by implanting/diffusing source region dopants into the collector regions. To achieve preferred device characteristics, the array of collector regions is formed to be diametrically opposite the array of emitter regions to thereby define a plurality of vertical IGBT cells.