Abstract: A fully differential sample and hold, switched-capacitor adder circuit is disclosed, where a single-ended and fully differential signals can be added together. Thus in one single operation, the adder circuit performs two functions conventionally performed by two separate circuits: converting the single-ended voltage signal into fully differential; and adding this converted differential signal to another differential signal. The adder circuit includes an operational amplifier, capacitors and switches for performing the operation. The circuit is economical when implemented in silicon.

Abstract: A method for checking parity on, for example, an Extended Industry Standard Architecture (EISA) bus. In a 32-bit information bus, four parity pins may be provided. During a first clock cycle the pins are all driven high and during a second clock cycle the pins are all driven low. This characteristic pattern is detected by a slave device and provides an indication that parity data will be transmitted on the four parity pins. After an indication of parity support the pins are provided with parity bits for error detection.

Abstract: A membrane switch comprises an upper flexible layers, separation layer and a lower conductive layer mounted on a support. The membrane switch is designed to absorb the noise created when a key is depressed and an operating block collides with the layers directly beneath it. By creating several holes in the one or more of the lower layers of the membrane switch, and optionally the support that geometrically surrounds the aperture of the separation layer, the colliding force of the operating block on the laminated membrane switch is dispersed and much of the noise is absorbed.

Abstract: A device for resolving deadlock between a local processor and system resources for access to a local store in a multiprocessor data processing system having high speed cache comprises an address storage device, deadlock resolution logic and a deadlock detector. The address storage device is coupled to the local bus for storing addresses in response a local store access signal on the system bus and for supply of the address to the cache controller. The detector is connected to the local bus and system bus to detect a deadlock condition. The deadlock resolution logic generates a sequence of control signals in response to the deadlock signal that resolves the deadlock condition. In particular, deadlocks are resolved by tristating the local buffer in response to the deadlock signal to disable external access signals from controlling the local bus to allow a local store access signal to gain control of the local bus.

Abstract: A scannable latch system comprises a plurality of scannable latches and clock driver circuit that allow at-speed testing of integrated circuits. Each scannable latch comprises a master latch, a slave latch and an auxiliary latch. The master latch is a two input latch capable of receiving data from two sources. The output of the master latch is coupled to the input of the slave and auxiliary latches. The clock driver circuitry receives a clock and control signals which are transformed into signals that operate the scannable latch in three different modes. In the normal mode, the slave latch is transparent and the data is held primarily in the master latch. In the scan mode, data may be shifted into the master, shifted out through the auxiliary latch, or shifted both in and out with a propagate function. Finally, in a test mode independent data values may be stored in the master latch and the slave latch.

Abstract: A staff scheduling data processing system and method schedules staff and management personnel at locations remote from a central location by applying central location policy to unique remote location data to insure the optimum staff schedule for each remote site. The system and method includes a data base for storing and retrieving information characterizing: central office policy; applicable labor requirements; tasks that need to be performed; skill levels required to perform tasks; resources that may confine or facilitate the scheduling of a task at a given time; relationships between tasks that will alter the placement or movement of a task on a schedule; employees with associated skill levels and priorities and availability; the employee's start-time and stop time, the percentage of an employee's time that it takes to work on a particular task, and the positive or negative slide in relation to the task's completion time by an employee.

Abstract: A magnetic tape cassette having a pair of spaced-apart reels rotatably mounted on a support wall. A length of tape has its opposite ends secured respectively to the two reels and its intermediate portion wound around the reels to form corresponding tape rolls whose diameters vary inversely as the tape is simultaneously unwound from one reel and wound onto the other. The two rolls have outer tape windings with recording surfaces thereon facing each other. Tape cleaning means is interposed between, and biased into contact with, the outer winding facing surfaces for continuously cleaning those surfaces as the tape is unwound from one reel and wound onto the other.

Abstract: The invention is directed to a solid, pyrotechnic composition as a base-bleed composition for reducing the base-drag of non-self-propelled projectiles. The composition comprises a oxygenated hydrocarbon component and an oxidizing agent component.